Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7440387 |
1 |
|
|
T23 |
1 |
|
T24 |
1050 |
|
T25 |
35953 |
| auto[1] |
5334287 |
1 |
|
|
T24 |
1008 |
|
T25 |
29925 |
|
T28 |
922 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10558208 |
1 |
|
|
T23 |
1 |
|
T24 |
1557 |
|
T25 |
54158 |
| auto[1] |
2216466 |
1 |
|
|
T24 |
501 |
|
T25 |
11720 |
|
T28 |
789 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7414583 |
1 |
|
|
T23 |
1 |
|
T24 |
1095 |
|
T25 |
37177 |
| auto[1] |
5360091 |
1 |
|
|
T24 |
963 |
|
T25 |
28701 |
|
T28 |
1022 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1575584 |
1 |
|
|
T24 |
295 |
|
T25 |
7883 |
|
T28 |
110 |
| auto[1] |
auto[0] |
auto[1] |
1111678 |
1 |
|
|
T24 |
314 |
|
T25 |
5632 |
|
T28 |
403 |
| auto[1] |
auto[1] |
auto[0] |
1568041 |
1 |
|
|
T24 |
167 |
|
T25 |
9098 |
|
T28 |
123 |
| auto[1] |
auto[1] |
auto[1] |
1104788 |
1 |
|
|
T24 |
187 |
|
T25 |
6088 |
|
T28 |
386 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |