Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7441455 |
1 |
|
|
T23 |
1 |
|
T24 |
1220 |
|
T25 |
37750 |
| auto[1] |
5333219 |
1 |
|
|
T24 |
838 |
|
T25 |
28128 |
|
T28 |
968 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10578465 |
1 |
|
|
T23 |
1 |
|
T24 |
1400 |
|
T25 |
54557 |
| auto[1] |
2196209 |
1 |
|
|
T24 |
658 |
|
T25 |
11321 |
|
T28 |
657 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7445891 |
1 |
|
|
T23 |
1 |
|
T24 |
822 |
|
T25 |
37441 |
| auto[1] |
5328783 |
1 |
|
|
T24 |
1236 |
|
T25 |
28437 |
|
T28 |
819 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1566804 |
1 |
|
|
T24 |
358 |
|
T25 |
8612 |
|
T28 |
116 |
| auto[1] |
auto[0] |
auto[1] |
1095629 |
1 |
|
|
T24 |
419 |
|
T25 |
5785 |
|
T28 |
357 |
| auto[1] |
auto[1] |
auto[0] |
1565770 |
1 |
|
|
T24 |
220 |
|
T25 |
8504 |
|
T28 |
46 |
| auto[1] |
auto[1] |
auto[1] |
1100580 |
1 |
|
|
T24 |
239 |
|
T25 |
5536 |
|
T28 |
300 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |