Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7442469 |
1 |
|
|
T23 |
1 |
|
T24 |
1000 |
|
T25 |
36739 |
| auto[1] |
5332205 |
1 |
|
|
T24 |
1058 |
|
T25 |
29139 |
|
T28 |
1076 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12090156 |
1 |
|
|
T23 |
1 |
|
T24 |
1857 |
|
T25 |
62147 |
| auto[1] |
684518 |
1 |
|
|
T24 |
201 |
|
T25 |
3731 |
|
T28 |
41 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7448782 |
1 |
|
|
T23 |
1 |
|
T24 |
976 |
|
T25 |
37153 |
| auto[1] |
5325892 |
1 |
|
|
T24 |
1082 |
|
T25 |
28725 |
|
T28 |
1071 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2329045 |
1 |
|
|
T24 |
499 |
|
T25 |
12054 |
|
T28 |
480 |
| auto[1] |
auto[0] |
auto[1] |
342696 |
1 |
|
|
T24 |
110 |
|
T25 |
1752 |
|
T28 |
23 |
| auto[1] |
auto[1] |
auto[0] |
2312329 |
1 |
|
|
T24 |
382 |
|
T25 |
12940 |
|
T28 |
550 |
| auto[1] |
auto[1] |
auto[1] |
341822 |
1 |
|
|
T24 |
91 |
|
T25 |
1979 |
|
T28 |
18 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |