Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7419987 |
1 |
|
|
T23 |
1 |
|
T24 |
1130 |
|
T25 |
36116 |
| auto[1] |
5354687 |
1 |
|
|
T24 |
928 |
|
T25 |
29762 |
|
T28 |
932 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12088743 |
1 |
|
|
T23 |
1 |
|
T24 |
1881 |
|
T25 |
62201 |
| auto[1] |
685931 |
1 |
|
|
T24 |
177 |
|
T25 |
3677 |
|
T28 |
45 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7430746 |
1 |
|
|
T23 |
1 |
|
T24 |
1072 |
|
T25 |
37070 |
| auto[1] |
5343928 |
1 |
|
|
T24 |
986 |
|
T25 |
28808 |
|
T28 |
1093 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2318684 |
1 |
|
|
T24 |
450 |
|
T25 |
12114 |
|
T28 |
588 |
| auto[1] |
auto[0] |
auto[1] |
341401 |
1 |
|
|
T24 |
95 |
|
T25 |
1814 |
|
T28 |
25 |
| auto[1] |
auto[1] |
auto[0] |
2339313 |
1 |
|
|
T24 |
359 |
|
T25 |
13017 |
|
T28 |
460 |
| auto[1] |
auto[1] |
auto[1] |
344530 |
1 |
|
|
T24 |
82 |
|
T25 |
1863 |
|
T28 |
20 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |