Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 940
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T757 /workspace/coverage/cover_reg_top/31.gpio_intr_test.2173929166 May 23 12:40:02 PM PDT 24 May 23 12:40:06 PM PDT 24 51953193 ps
T758 /workspace/coverage/cover_reg_top/14.gpio_intr_test.2753479300 May 23 12:39:35 PM PDT 24 May 23 12:39:37 PM PDT 24 46793412 ps
T759 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.257476704 May 23 12:39:07 PM PDT 24 May 23 12:39:11 PM PDT 24 78049710 ps
T760 /workspace/coverage/cover_reg_top/0.gpio_intr_test.3675514014 May 23 12:39:00 PM PDT 24 May 23 12:39:02 PM PDT 24 27255463 ps
T761 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.1876158345 May 23 12:39:00 PM PDT 24 May 23 12:39:03 PM PDT 24 116031994 ps
T762 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.1675747826 May 23 12:39:19 PM PDT 24 May 23 12:39:21 PM PDT 24 253271273 ps
T53 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.2604764164 May 23 12:39:22 PM PDT 24 May 23 12:39:25 PM PDT 24 236010741 ps
T763 /workspace/coverage/cover_reg_top/4.gpio_intr_test.3683928412 May 23 12:39:10 PM PDT 24 May 23 12:39:13 PM PDT 24 17090530 ps
T764 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2300611579 May 23 12:39:10 PM PDT 24 May 23 12:39:13 PM PDT 24 47143364 ps
T765 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3089203809 May 23 12:39:21 PM PDT 24 May 23 12:39:23 PM PDT 24 24595427 ps
T54 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.2371339047 May 23 12:39:49 PM PDT 24 May 23 12:39:53 PM PDT 24 462414245 ps
T766 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2312642176 May 23 12:39:21 PM PDT 24 May 23 12:39:23 PM PDT 24 113321883 ps
T767 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.501771484 May 23 12:39:32 PM PDT 24 May 23 12:39:34 PM PDT 24 15233275 ps
T768 /workspace/coverage/cover_reg_top/26.gpio_intr_test.15203281 May 23 12:40:01 PM PDT 24 May 23 12:40:05 PM PDT 24 36019975 ps
T769 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.2438834549 May 23 12:39:46 PM PDT 24 May 23 12:39:48 PM PDT 24 53037430 ps
T770 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.2617118344 May 23 12:39:49 PM PDT 24 May 23 12:39:53 PM PDT 24 16281470 ps
T771 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2540472937 May 23 12:39:34 PM PDT 24 May 23 12:39:37 PM PDT 24 36333611 ps
T49 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.4013751869 May 23 12:39:20 PM PDT 24 May 23 12:39:23 PM PDT 24 709219766 ps
T772 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1446016603 May 23 12:39:09 PM PDT 24 May 23 12:39:14 PM PDT 24 899646079 ps
T773 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.4133600946 May 23 12:39:45 PM PDT 24 May 23 12:39:49 PM PDT 24 422392654 ps
T774 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1276501984 May 23 12:39:18 PM PDT 24 May 23 12:39:20 PM PDT 24 22780997 ps
T775 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.2604272539 May 23 12:39:32 PM PDT 24 May 23 12:39:35 PM PDT 24 34863414 ps
T776 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.257584738 May 23 12:39:50 PM PDT 24 May 23 12:39:54 PM PDT 24 64543121 ps
T777 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.2694255835 May 23 12:39:47 PM PDT 24 May 23 12:39:52 PM PDT 24 202530934 ps
T778 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.660448863 May 23 12:38:55 PM PDT 24 May 23 12:38:57 PM PDT 24 100157010 ps
T52 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2951324834 May 23 12:39:47 PM PDT 24 May 23 12:39:51 PM PDT 24 146905927 ps
T779 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.2615112589 May 23 12:39:48 PM PDT 24 May 23 12:39:53 PM PDT 24 43518219 ps
T780 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.567754333 May 23 12:39:45 PM PDT 24 May 23 12:39:46 PM PDT 24 13319875 ps
T781 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.3903891381 May 23 12:39:07 PM PDT 24 May 23 12:39:10 PM PDT 24 28194589 ps
T782 /workspace/coverage/cover_reg_top/3.gpio_intr_test.4289104893 May 23 12:39:08 PM PDT 24 May 23 12:39:11 PM PDT 24 45485163 ps
T783 /workspace/coverage/cover_reg_top/36.gpio_intr_test.850169124 May 23 12:40:01 PM PDT 24 May 23 12:40:04 PM PDT 24 64432938 ps
T784 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3395390201 May 23 12:40:02 PM PDT 24 May 23 12:40:07 PM PDT 24 95813772 ps
T785 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1528307642 May 23 12:39:06 PM PDT 24 May 23 12:39:10 PM PDT 24 170630331 ps
T786 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1016821030 May 23 12:38:55 PM PDT 24 May 23 12:38:57 PM PDT 24 77716785 ps
T787 /workspace/coverage/cover_reg_top/7.gpio_intr_test.170309181 May 23 12:39:23 PM PDT 24 May 23 12:39:25 PM PDT 24 18509210 ps
T788 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.167061091 May 23 12:39:46 PM PDT 24 May 23 12:39:49 PM PDT 24 264544297 ps
T789 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.2963185688 May 23 12:39:35 PM PDT 24 May 23 12:39:38 PM PDT 24 64706880 ps
T790 /workspace/coverage/cover_reg_top/29.gpio_intr_test.26264425 May 23 12:40:04 PM PDT 24 May 23 12:40:08 PM PDT 24 48860679 ps
T791 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.390682259 May 23 12:39:31 PM PDT 24 May 23 12:39:33 PM PDT 24 33938326 ps
T792 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.3084964216 May 23 12:39:27 PM PDT 24 May 23 12:39:29 PM PDT 24 108665639 ps
T793 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1797202885 May 23 12:39:20 PM PDT 24 May 23 12:39:22 PM PDT 24 21657976 ps
T794 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.3586499751 May 23 12:39:36 PM PDT 24 May 23 12:39:40 PM PDT 24 37006107 ps
T795 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.1779482590 May 23 12:39:09 PM PDT 24 May 23 12:39:14 PM PDT 24 439010687 ps
T796 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.2476511664 May 23 12:39:35 PM PDT 24 May 23 12:39:39 PM PDT 24 213050147 ps
T797 /workspace/coverage/cover_reg_top/39.gpio_intr_test.3802932457 May 23 12:40:03 PM PDT 24 May 23 12:40:08 PM PDT 24 39514784 ps
T798 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2281761697 May 23 12:39:43 PM PDT 24 May 23 12:39:45 PM PDT 24 43177124 ps
T799 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.1639037793 May 23 12:39:06 PM PDT 24 May 23 12:39:09 PM PDT 24 126618931 ps
T800 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.610650738 May 23 12:39:19 PM PDT 24 May 23 12:39:21 PM PDT 24 30641232 ps
T96 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.3013315926 May 23 12:39:15 PM PDT 24 May 23 12:39:17 PM PDT 24 15695698 ps
T801 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.1920797599 May 23 12:39:08 PM PDT 24 May 23 12:39:11 PM PDT 24 168936817 ps
T802 /workspace/coverage/cover_reg_top/32.gpio_intr_test.420532470 May 23 12:40:02 PM PDT 24 May 23 12:40:06 PM PDT 24 18348096 ps
T803 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.2583019073 May 23 12:39:20 PM PDT 24 May 23 12:39:22 PM PDT 24 31934530 ps
T804 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3794674825 May 23 12:39:08 PM PDT 24 May 23 12:39:12 PM PDT 24 57008138 ps
T805 /workspace/coverage/cover_reg_top/5.gpio_intr_test.2201823809 May 23 12:39:22 PM PDT 24 May 23 12:39:25 PM PDT 24 46359524 ps
T806 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.3363158307 May 23 12:39:35 PM PDT 24 May 23 12:39:38 PM PDT 24 32559320 ps
T807 /workspace/coverage/cover_reg_top/25.gpio_intr_test.2283888416 May 23 12:40:01 PM PDT 24 May 23 12:40:03 PM PDT 24 53933196 ps
T808 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.3746268245 May 23 12:39:35 PM PDT 24 May 23 12:39:39 PM PDT 24 499148855 ps
T809 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.897218590 May 23 12:39:11 PM PDT 24 May 23 12:39:14 PM PDT 24 248254526 ps
T810 /workspace/coverage/cover_reg_top/23.gpio_intr_test.1098216904 May 23 12:40:02 PM PDT 24 May 23 12:40:07 PM PDT 24 32860228 ps
T811 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.367882877 May 23 12:38:58 PM PDT 24 May 23 12:39:00 PM PDT 24 137980480 ps
T812 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1497522530 May 23 12:39:00 PM PDT 24 May 23 12:39:03 PM PDT 24 105995512 ps
T813 /workspace/coverage/cover_reg_top/6.gpio_intr_test.1064465101 May 23 12:39:19 PM PDT 24 May 23 12:39:21 PM PDT 24 41635365 ps
T814 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.3052366687 May 23 12:39:27 PM PDT 24 May 23 12:39:29 PM PDT 24 258548653 ps
T815 /workspace/coverage/cover_reg_top/30.gpio_intr_test.1777625981 May 23 12:40:03 PM PDT 24 May 23 12:40:08 PM PDT 24 104107030 ps
T816 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1315410728 May 23 12:39:49 PM PDT 24 May 23 12:39:53 PM PDT 24 33861144 ps
T817 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.456826657 May 23 12:39:22 PM PDT 24 May 23 12:39:25 PM PDT 24 30301313 ps
T818 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.715366652 May 23 12:39:42 PM PDT 24 May 23 12:39:44 PM PDT 24 13513049 ps
T819 /workspace/coverage/cover_reg_top/15.gpio_intr_test.4102305905 May 23 12:39:43 PM PDT 24 May 23 12:39:45 PM PDT 24 14449746 ps
T820 /workspace/coverage/cover_reg_top/41.gpio_intr_test.3490292066 May 23 12:40:03 PM PDT 24 May 23 12:40:08 PM PDT 24 87627919 ps
T821 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3639219300 May 23 12:39:09 PM PDT 24 May 23 12:39:13 PM PDT 24 15671789 ps
T822 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.2179808589 May 23 12:39:10 PM PDT 24 May 23 12:39:14 PM PDT 24 219395695 ps
T823 /workspace/coverage/cover_reg_top/43.gpio_intr_test.4191291233 May 23 12:40:00 PM PDT 24 May 23 12:40:03 PM PDT 24 18601061 ps
T824 /workspace/coverage/cover_reg_top/44.gpio_intr_test.2341327724 May 23 12:40:04 PM PDT 24 May 23 12:40:09 PM PDT 24 43479148 ps
T825 /workspace/coverage/cover_reg_top/38.gpio_intr_test.2915104146 May 23 12:40:05 PM PDT 24 May 23 12:40:09 PM PDT 24 21384049 ps
T826 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.1069831002 May 23 12:39:20 PM PDT 24 May 23 12:39:23 PM PDT 24 39423698 ps
T827 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.3848656513 May 23 12:39:18 PM PDT 24 May 23 12:39:21 PM PDT 24 480315022 ps
T828 /workspace/coverage/cover_reg_top/18.gpio_intr_test.1744762418 May 23 12:39:50 PM PDT 24 May 23 12:39:53 PM PDT 24 83809209 ps
T829 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2503559328 May 23 12:39:42 PM PDT 24 May 23 12:39:46 PM PDT 24 453871624 ps
T830 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.3227439943 May 23 12:39:18 PM PDT 24 May 23 12:39:21 PM PDT 24 79442387 ps
T97 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.1412886538 May 23 12:39:15 PM PDT 24 May 23 12:39:17 PM PDT 24 42905086 ps
T831 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1072128208 May 23 12:39:00 PM PDT 24 May 23 12:39:02 PM PDT 24 142930658 ps
T832 /workspace/coverage/cover_reg_top/46.gpio_intr_test.593500122 May 23 12:40:03 PM PDT 24 May 23 12:40:07 PM PDT 24 12387961 ps
T833 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3625074808 May 23 12:39:45 PM PDT 24 May 23 12:39:47 PM PDT 24 13520300 ps
T834 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1372242274 May 23 12:39:46 PM PDT 24 May 23 12:39:50 PM PDT 24 69854984 ps
T835 /workspace/coverage/cover_reg_top/33.gpio_intr_test.170936920 May 23 12:40:00 PM PDT 24 May 23 12:40:03 PM PDT 24 20309469 ps
T836 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.434961512 May 23 12:39:35 PM PDT 24 May 23 12:39:38 PM PDT 24 12891418 ps
T837 /workspace/coverage/cover_reg_top/42.gpio_intr_test.304784253 May 23 12:40:02 PM PDT 24 May 23 12:40:07 PM PDT 24 29541941 ps
T838 /workspace/coverage/cover_reg_top/1.gpio_intr_test.1461986366 May 23 12:39:11 PM PDT 24 May 23 12:39:14 PM PDT 24 11667718 ps
T839 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3202160442 May 23 12:39:48 PM PDT 24 May 23 12:39:52 PM PDT 24 100750098 ps
T840 /workspace/coverage/cover_reg_top/34.gpio_intr_test.317442484 May 23 12:40:00 PM PDT 24 May 23 12:40:03 PM PDT 24 48922514 ps
T841 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1082668048 May 23 12:41:24 PM PDT 24 May 23 12:41:27 PM PDT 24 1500793522 ps
T842 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3794427198 May 23 12:41:16 PM PDT 24 May 23 12:41:19 PM PDT 24 117790892 ps
T843 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2817464764 May 23 12:41:29 PM PDT 24 May 23 12:41:32 PM PDT 24 49027972 ps
T844 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2823657346 May 23 12:41:24 PM PDT 24 May 23 12:41:27 PM PDT 24 46745970 ps
T845 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3269748104 May 23 12:41:37 PM PDT 24 May 23 12:41:39 PM PDT 24 53059414 ps
T846 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1595477055 May 23 12:41:30 PM PDT 24 May 23 12:41:33 PM PDT 24 121904448 ps
T847 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.429651534 May 23 12:41:39 PM PDT 24 May 23 12:41:42 PM PDT 24 229261055 ps
T848 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.489496031 May 23 12:41:23 PM PDT 24 May 23 12:41:26 PM PDT 24 113874051 ps
T849 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1572560312 May 23 12:41:28 PM PDT 24 May 23 12:41:31 PM PDT 24 70973499 ps
T850 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.652818692 May 23 12:41:30 PM PDT 24 May 23 12:41:32 PM PDT 24 33713571 ps
T851 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3363116013 May 23 12:41:37 PM PDT 24 May 23 12:41:39 PM PDT 24 129483041 ps
T852 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2805362345 May 23 12:41:24 PM PDT 24 May 23 12:41:27 PM PDT 24 182666734 ps
T853 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1567523804 May 23 12:41:26 PM PDT 24 May 23 12:41:30 PM PDT 24 258075556 ps
T854 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.857337783 May 23 12:41:37 PM PDT 24 May 23 12:41:39 PM PDT 24 130031621 ps
T855 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3842832112 May 23 12:41:29 PM PDT 24 May 23 12:41:32 PM PDT 24 101614319 ps
T856 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3853765110 May 23 12:41:28 PM PDT 24 May 23 12:41:32 PM PDT 24 219086814 ps
T857 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1538141698 May 23 12:41:25 PM PDT 24 May 23 12:41:29 PM PDT 24 197396525 ps
T858 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3741276505 May 23 12:41:28 PM PDT 24 May 23 12:41:31 PM PDT 24 196974375 ps
T859 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3407957745 May 23 12:41:27 PM PDT 24 May 23 12:41:31 PM PDT 24 114759325 ps
T860 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2095973043 May 23 12:41:39 PM PDT 24 May 23 12:41:42 PM PDT 24 44295424 ps
T861 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3424367395 May 23 12:41:23 PM PDT 24 May 23 12:41:25 PM PDT 24 127031467 ps
T862 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.494144840 May 23 12:41:37 PM PDT 24 May 23 12:41:39 PM PDT 24 36663996 ps
T863 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2451665006 May 23 12:41:29 PM PDT 24 May 23 12:41:32 PM PDT 24 232550388 ps
T864 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3288703917 May 23 12:41:26 PM PDT 24 May 23 12:41:30 PM PDT 24 46079493 ps
T865 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1530418190 May 23 12:41:24 PM PDT 24 May 23 12:41:27 PM PDT 24 167736385 ps
T866 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2853352071 May 23 12:41:25 PM PDT 24 May 23 12:41:28 PM PDT 24 77914653 ps
T867 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2699802859 May 23 12:41:24 PM PDT 24 May 23 12:41:28 PM PDT 24 153392723 ps
T868 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3180608822 May 23 12:41:22 PM PDT 24 May 23 12:41:24 PM PDT 24 98617783 ps
T869 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3929994581 May 23 12:41:37 PM PDT 24 May 23 12:41:39 PM PDT 24 470936347 ps
T870 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.644772374 May 23 12:41:11 PM PDT 24 May 23 12:41:14 PM PDT 24 192254086 ps
T871 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3622701057 May 23 12:41:24 PM PDT 24 May 23 12:41:26 PM PDT 24 225147447 ps
T872 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.482526708 May 23 12:41:33 PM PDT 24 May 23 12:41:35 PM PDT 24 166592131 ps
T873 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.4063610129 May 23 12:41:24 PM PDT 24 May 23 12:41:28 PM PDT 24 363664803 ps
T874 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.4017215332 May 23 12:41:28 PM PDT 24 May 23 12:41:31 PM PDT 24 180338641 ps
T875 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2273241579 May 23 12:41:22 PM PDT 24 May 23 12:41:25 PM PDT 24 54830868 ps
T876 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2309976170 May 23 12:41:39 PM PDT 24 May 23 12:41:42 PM PDT 24 298517127 ps
T877 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2425925941 May 23 12:41:38 PM PDT 24 May 23 12:41:41 PM PDT 24 245236110 ps
T878 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2384965081 May 23 12:41:28 PM PDT 24 May 23 12:41:31 PM PDT 24 479790064 ps
T879 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1945126604 May 23 12:41:38 PM PDT 24 May 23 12:41:41 PM PDT 24 61851596 ps
T880 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1258485273 May 23 12:41:39 PM PDT 24 May 23 12:41:42 PM PDT 24 50986347 ps
T881 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3168919785 May 23 12:41:39 PM PDT 24 May 23 12:41:42 PM PDT 24 59968745 ps
T882 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1243286344 May 23 12:41:24 PM PDT 24 May 23 12:41:28 PM PDT 24 662344475 ps
T883 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2003665187 May 23 12:41:24 PM PDT 24 May 23 12:41:27 PM PDT 24 469570651 ps
T884 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1525061973 May 23 12:41:44 PM PDT 24 May 23 12:41:46 PM PDT 24 51114839 ps
T885 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3871467334 May 23 12:41:24 PM PDT 24 May 23 12:41:28 PM PDT 24 157265283 ps
T886 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3334210183 May 23 12:41:25 PM PDT 24 May 23 12:41:29 PM PDT 24 90318104 ps
T887 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.916980803 May 23 12:41:29 PM PDT 24 May 23 12:41:32 PM PDT 24 193931773 ps
T888 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.816212033 May 23 12:41:26 PM PDT 24 May 23 12:41:29 PM PDT 24 62048858 ps
T889 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1292698187 May 23 12:41:36 PM PDT 24 May 23 12:41:37 PM PDT 24 34958213 ps
T890 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2448993491 May 23 12:41:32 PM PDT 24 May 23 12:41:35 PM PDT 24 37361795 ps
T891 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.390559678 May 23 12:41:29 PM PDT 24 May 23 12:41:32 PM PDT 24 51904031 ps
T892 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.54927318 May 23 12:41:23 PM PDT 24 May 23 12:41:26 PM PDT 24 283464731 ps
T893 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.2606037808 May 23 12:41:15 PM PDT 24 May 23 12:41:18 PM PDT 24 35497825 ps
T894 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2697413284 May 23 12:41:37 PM PDT 24 May 23 12:41:40 PM PDT 24 467569915 ps
T895 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3312682173 May 23 12:41:33 PM PDT 24 May 23 12:41:35 PM PDT 24 35443761 ps
T896 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3189730815 May 23 12:41:23 PM PDT 24 May 23 12:41:26 PM PDT 24 161948916 ps
T897 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.137960555 May 23 12:41:38 PM PDT 24 May 23 12:41:41 PM PDT 24 45512424 ps
T898 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.708684017 May 23 12:41:22 PM PDT 24 May 23 12:41:24 PM PDT 24 160666318 ps
T899 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.3728038118 May 23 12:41:37 PM PDT 24 May 23 12:41:39 PM PDT 24 56698832 ps
T900 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1336278138 May 23 12:41:22 PM PDT 24 May 23 12:41:24 PM PDT 24 49653191 ps
T901 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3302196583 May 23 12:41:32 PM PDT 24 May 23 12:41:35 PM PDT 24 232148635 ps
T902 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1372952951 May 23 12:41:25 PM PDT 24 May 23 12:41:29 PM PDT 24 28849608 ps
T903 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2148815308 May 23 12:41:23 PM PDT 24 May 23 12:41:26 PM PDT 24 91691231 ps
T904 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3979890148 May 23 12:41:23 PM PDT 24 May 23 12:41:25 PM PDT 24 59119811 ps
T905 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3685106993 May 23 12:41:37 PM PDT 24 May 23 12:41:40 PM PDT 24 40480685 ps
T906 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1294813566 May 23 12:41:22 PM PDT 24 May 23 12:41:25 PM PDT 24 36794526 ps
T907 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3753962449 May 23 12:41:39 PM PDT 24 May 23 12:41:42 PM PDT 24 40488979 ps
T908 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.72400681 May 23 12:41:39 PM PDT 24 May 23 12:41:42 PM PDT 24 133982943 ps
T909 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.459489841 May 23 12:41:31 PM PDT 24 May 23 12:41:34 PM PDT 24 147094785 ps
T910 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.55626552 May 23 12:41:23 PM PDT 24 May 23 12:41:26 PM PDT 24 80490535 ps
T911 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4179954810 May 23 12:41:38 PM PDT 24 May 23 12:41:41 PM PDT 24 160406571 ps
T912 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1033502057 May 23 12:41:29 PM PDT 24 May 23 12:41:32 PM PDT 24 87700908 ps
T913 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2743991871 May 23 12:41:25 PM PDT 24 May 23 12:41:28 PM PDT 24 33715527 ps
T914 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.169915108 May 23 12:41:14 PM PDT 24 May 23 12:41:18 PM PDT 24 403814730 ps
T915 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.689887222 May 23 12:41:26 PM PDT 24 May 23 12:41:30 PM PDT 24 87026407 ps
T916 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.287338795 May 23 12:41:26 PM PDT 24 May 23 12:41:29 PM PDT 24 40603143 ps
T917 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.363571659 May 23 12:41:24 PM PDT 24 May 23 12:41:28 PM PDT 24 46545563 ps
T918 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2433609954 May 23 12:41:25 PM PDT 24 May 23 12:41:28 PM PDT 24 199910533 ps
T919 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3172795381 May 23 12:41:15 PM PDT 24 May 23 12:41:18 PM PDT 24 271669041 ps
T920 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1088656049 May 23 12:41:32 PM PDT 24 May 23 12:41:35 PM PDT 24 159532423 ps
T921 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.572295271 May 23 12:41:30 PM PDT 24 May 23 12:41:33 PM PDT 24 48918426 ps
T922 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.718911296 May 23 12:41:25 PM PDT 24 May 23 12:41:28 PM PDT 24 61800517 ps
T923 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.466116352 May 23 12:41:38 PM PDT 24 May 23 12:41:41 PM PDT 24 621083248 ps
T924 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.4223378818 May 23 12:41:36 PM PDT 24 May 23 12:41:39 PM PDT 24 51885574 ps
T925 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4129455280 May 23 12:41:24 PM PDT 24 May 23 12:41:28 PM PDT 24 147472112 ps
T926 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3386843982 May 23 12:41:28 PM PDT 24 May 23 12:41:31 PM PDT 24 96270200 ps
T927 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.638468218 May 23 12:41:43 PM PDT 24 May 23 12:41:45 PM PDT 24 37109463 ps
T928 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.431823197 May 23 12:41:36 PM PDT 24 May 23 12:41:38 PM PDT 24 30892136 ps
T929 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1440357998 May 23 12:41:28 PM PDT 24 May 23 12:41:31 PM PDT 24 66376284 ps
T930 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1469792428 May 23 12:41:36 PM PDT 24 May 23 12:41:38 PM PDT 24 36373503 ps
T931 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.537420874 May 23 12:41:38 PM PDT 24 May 23 12:41:42 PM PDT 24 310194596 ps
T932 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1880189960 May 23 12:41:25 PM PDT 24 May 23 12:41:29 PM PDT 24 120183246 ps
T933 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3061386461 May 23 12:41:26 PM PDT 24 May 23 12:41:30 PM PDT 24 159898646 ps
T934 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.683526026 May 23 12:41:23 PM PDT 24 May 23 12:41:26 PM PDT 24 60064986 ps
T935 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2682976781 May 23 12:41:37 PM PDT 24 May 23 12:41:40 PM PDT 24 144642789 ps
T936 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3907263011 May 23 12:41:47 PM PDT 24 May 23 12:41:49 PM PDT 24 74919753 ps
T937 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.459491898 May 23 12:41:30 PM PDT 24 May 23 12:41:32 PM PDT 24 166154329 ps
T938 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3936572584 May 23 12:41:24 PM PDT 24 May 23 12:41:27 PM PDT 24 100598935 ps
T939 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2879675484 May 23 12:41:24 PM PDT 24 May 23 12:41:27 PM PDT 24 50787560 ps
T940 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3688065726 May 23 12:41:28 PM PDT 24 May 23 12:41:31 PM PDT 24 117250461 ps

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.605611207
Short name T28
Test name
Test status
Simulation time 351283050 ps
CPU time 4.05 seconds
Started May 23 12:42:50 PM PDT 24
Finished May 23 12:42:56 PM PDT 24
Peak memory 197848 kb
Host smart-ab5e7038-7ff2-44d7-a5fa-10ea26f5255f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605611207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ran
dom_long_reg_writes_reg_reads.605611207
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.3941283561
Short name T55
Test name
Test status
Simulation time 140027592 ps
CPU time 2.9 seconds
Started May 23 12:43:08 PM PDT 24
Finished May 23 12:43:14 PM PDT 24
Peak memory 197912 kb
Host smart-03593995-ffed-4ab1-81cd-d4d19cf2e93e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941283561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.3941283561
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.557964587
Short name T44
Test name
Test status
Simulation time 125244598 ps
CPU time 1.34 seconds
Started May 23 12:42:05 PM PDT 24
Finished May 23 12:42:08 PM PDT 24
Peak memory 196344 kb
Host smart-c1a78d3f-7ae2-4a5d-a8fd-9a1eda61fc8e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557964587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup_
pulldown.557964587
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.874579932
Short name T4
Test name
Test status
Simulation time 23818954733 ps
CPU time 324.42 seconds
Started May 23 12:42:49 PM PDT 24
Finished May 23 12:48:16 PM PDT 24
Peak memory 198044 kb
Host smart-0f34b186-ca95-4745-bff7-5c501f986a06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=874579932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.874579932
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.1457758370
Short name T41
Test name
Test status
Simulation time 44048289 ps
CPU time 0.79 seconds
Started May 23 12:41:51 PM PDT 24
Finished May 23 12:41:55 PM PDT 24
Peak memory 213512 kb
Host smart-139959a5-c63f-4ff0-919b-9bd1765df0cd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457758370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.1457758370
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.2227851314
Short name T85
Test name
Test status
Simulation time 60129385 ps
CPU time 0.58 seconds
Started May 23 12:39:34 PM PDT 24
Finished May 23 12:39:36 PM PDT 24
Peak memory 193104 kb
Host smart-66732d9a-c9cd-441f-a6a2-7b13e1411a3c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227851314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.2227851314
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.2210272107
Short name T38
Test name
Test status
Simulation time 135496953 ps
CPU time 1.63 seconds
Started May 23 12:39:19 PM PDT 24
Finished May 23 12:39:22 PM PDT 24
Peak memory 197984 kb
Host smart-f8672615-fb2f-48b1-a5d6-31fd889f5e02
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210272107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.2210272107
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/4.gpio_alert_test.1494181970
Short name T23
Test name
Test status
Simulation time 36909000 ps
CPU time 0.54 seconds
Started May 23 12:42:01 PM PDT 24
Finished May 23 12:42:02 PM PDT 24
Peak memory 194568 kb
Host smart-2e26eb8a-d0cd-418b-9357-a1d492d0e26b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494181970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.1494181970
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.4013751869
Short name T49
Test name
Test status
Simulation time 709219766 ps
CPU time 1.5 seconds
Started May 23 12:39:20 PM PDT 24
Finished May 23 12:39:23 PM PDT 24
Peak memory 197840 kb
Host smart-eadc49fc-0318-4efb-8d27-cc0356cf4815
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013751869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.4013751869
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3509250383
Short name T95
Test name
Test status
Simulation time 20452094 ps
CPU time 0.67 seconds
Started May 23 12:39:01 PM PDT 24
Finished May 23 12:39:03 PM PDT 24
Peak memory 194180 kb
Host smart-95cef7ff-84e6-4402-9ff1-67a1142fe871
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509250383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.3509250383
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.2556449634
Short name T104
Test name
Test status
Simulation time 32779899 ps
CPU time 0.8 seconds
Started May 23 12:39:04 PM PDT 24
Finished May 23 12:39:06 PM PDT 24
Peak memory 196024 kb
Host smart-51b44e0e-c213-4f80-9949-d018f9b6b6c4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556449634 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.2556449634
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/default/12.gpio_full_random.875863526
Short name T2
Test name
Test status
Simulation time 28108340 ps
CPU time 0.66 seconds
Started May 23 12:42:18 PM PDT 24
Finished May 23 12:42:20 PM PDT 24
Peak memory 195184 kb
Host smart-b50bdcc7-88ad-4dca-a3ad-82c63db1eaab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875863526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.875863526
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.2604764164
Short name T53
Test name
Test status
Simulation time 236010741 ps
CPU time 1.24 seconds
Started May 23 12:39:22 PM PDT 24
Finished May 23 12:39:25 PM PDT 24
Peak memory 197876 kb
Host smart-550ddfb3-7ec1-414f-a38c-d9c1c652d9f1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604764164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.2604764164
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.428852975
Short name T92
Test name
Test status
Simulation time 81912504 ps
CPU time 2.9 seconds
Started May 23 12:39:00 PM PDT 24
Finished May 23 12:39:05 PM PDT 24
Peak memory 196176 kb
Host smart-3ae94fd9-3637-43c8-b4ea-2b43d197ecf4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428852975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.428852975
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1811075318
Short name T94
Test name
Test status
Simulation time 13785366 ps
CPU time 0.63 seconds
Started May 23 12:38:57 PM PDT 24
Finished May 23 12:38:59 PM PDT 24
Peak memory 194496 kb
Host smart-592c55f6-5bd7-4611-a0fc-d30ede16c76b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811075318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.1811075318
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1497522530
Short name T812
Test name
Test status
Simulation time 105995512 ps
CPU time 1.09 seconds
Started May 23 12:39:00 PM PDT 24
Finished May 23 12:39:03 PM PDT 24
Peak memory 197880 kb
Host smart-326075ba-b115-4f7e-b5ed-e73547241707
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497522530 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.1497522530
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.1876158345
Short name T761
Test name
Test status
Simulation time 116031994 ps
CPU time 0.59 seconds
Started May 23 12:39:00 PM PDT 24
Finished May 23 12:39:03 PM PDT 24
Peak memory 195232 kb
Host smart-f1e4278b-c104-4118-9b72-54449d56500d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876158345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.1876158345
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.3675514014
Short name T760
Test name
Test status
Simulation time 27255463 ps
CPU time 0.64 seconds
Started May 23 12:39:00 PM PDT 24
Finished May 23 12:39:02 PM PDT 24
Peak memory 193496 kb
Host smart-f7ac1f95-6a9d-4b0a-bda1-f716abde6edc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675514014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.3675514014
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.49060026
Short name T718
Test name
Test status
Simulation time 42225583 ps
CPU time 2.09 seconds
Started May 23 12:39:04 PM PDT 24
Finished May 23 12:39:08 PM PDT 24
Peak memory 197824 kb
Host smart-7a7229a1-ca4f-49f4-beef-dba5cc9df711
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49060026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.49060026
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1016821030
Short name T786
Test name
Test status
Simulation time 77716785 ps
CPU time 0.85 seconds
Started May 23 12:38:55 PM PDT 24
Finished May 23 12:38:57 PM PDT 24
Peak memory 196812 kb
Host smart-59ff605f-cbbd-4f8a-a300-99a1f21ecba7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016821030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.1016821030
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.3269649884
Short name T752
Test name
Test status
Simulation time 169131684 ps
CPU time 0.68 seconds
Started May 23 12:38:55 PM PDT 24
Finished May 23 12:38:57 PM PDT 24
Peak memory 194560 kb
Host smart-a7352d58-58e3-4a89-ba48-6c05d58b90ac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269649884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.3269649884
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.1639037793
Short name T799
Test name
Test status
Simulation time 126618931 ps
CPU time 1.42 seconds
Started May 23 12:39:06 PM PDT 24
Finished May 23 12:39:09 PM PDT 24
Peak memory 197716 kb
Host smart-cce116dc-49aa-4593-a8c2-a2e32c832733
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639037793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.1639037793
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2636147052
Short name T742
Test name
Test status
Simulation time 43225994 ps
CPU time 0.62 seconds
Started May 23 12:39:05 PM PDT 24
Finished May 23 12:39:07 PM PDT 24
Peak memory 194368 kb
Host smart-47700266-bd98-46da-bc76-2fe4b8a2c8fd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636147052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.2636147052
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.367882877
Short name T811
Test name
Test status
Simulation time 137980480 ps
CPU time 1.01 seconds
Started May 23 12:38:58 PM PDT 24
Finished May 23 12:39:00 PM PDT 24
Peak memory 197800 kb
Host smart-ef0ee5cd-a633-4443-b1ff-2b8d18162ebc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367882877 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.367882877
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.3244565569
Short name T748
Test name
Test status
Simulation time 23107935 ps
CPU time 0.58 seconds
Started May 23 12:39:04 PM PDT 24
Finished May 23 12:39:06 PM PDT 24
Peak memory 194580 kb
Host smart-d9fab1fe-baa0-42fb-8600-eff016651fcb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244565569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.3244565569
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.1461986366
Short name T838
Test name
Test status
Simulation time 11667718 ps
CPU time 0.58 seconds
Started May 23 12:39:11 PM PDT 24
Finished May 23 12:39:14 PM PDT 24
Peak memory 194184 kb
Host smart-1b35ad00-66b3-4752-a085-3af4d7ac7e40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461986366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.1461986366
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.660448863
Short name T778
Test name
Test status
Simulation time 100157010 ps
CPU time 0.63 seconds
Started May 23 12:38:55 PM PDT 24
Finished May 23 12:38:57 PM PDT 24
Peak memory 194808 kb
Host smart-05ddc78d-aae7-49dc-9f61-4e1aa727bc9a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660448863 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.gpio_same_csr_outstanding.660448863
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.1914845805
Short name T739
Test name
Test status
Simulation time 76050261 ps
CPU time 1.27 seconds
Started May 23 12:39:07 PM PDT 24
Finished May 23 12:39:10 PM PDT 24
Peak memory 197932 kb
Host smart-d7e4a893-76ba-414a-95e8-8595e96470e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914845805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.1914845805
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1072128208
Short name T831
Test name
Test status
Simulation time 142930658 ps
CPU time 0.84 seconds
Started May 23 12:39:00 PM PDT 24
Finished May 23 12:39:02 PM PDT 24
Peak memory 197028 kb
Host smart-8ca778a9-83b8-4bf0-bd3d-51d25a48a807
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072128208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.1072128208
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.3052366687
Short name T814
Test name
Test status
Simulation time 258548653 ps
CPU time 0.86 seconds
Started May 23 12:39:27 PM PDT 24
Finished May 23 12:39:29 PM PDT 24
Peak memory 197868 kb
Host smart-e5d56e6c-7a1e-416b-9b04-99c3814252cc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052366687 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.3052366687
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.35383679
Short name T106
Test name
Test status
Simulation time 43267779 ps
CPU time 0.58 seconds
Started May 23 12:39:25 PM PDT 24
Finished May 23 12:39:27 PM PDT 24
Peak memory 193728 kb
Host smart-d3f79342-25df-4ac0-ac96-44a456501dc1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35383679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_
csr_rw.35383679
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.1072810143
Short name T754
Test name
Test status
Simulation time 15712872 ps
CPU time 0.69 seconds
Started May 23 12:39:35 PM PDT 24
Finished May 23 12:39:38 PM PDT 24
Peak memory 193396 kb
Host smart-52138276-1129-435f-898b-be743c43c29f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072810143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.1072810143
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.2962889383
Short name T91
Test name
Test status
Simulation time 74144257 ps
CPU time 0.63 seconds
Started May 23 12:39:22 PM PDT 24
Finished May 23 12:39:25 PM PDT 24
Peak memory 194580 kb
Host smart-65d4dd23-8d89-4f73-8397-1355397ed4f8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962889383 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.2962889383
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.3746268245
Short name T808
Test name
Test status
Simulation time 499148855 ps
CPU time 2.62 seconds
Started May 23 12:39:35 PM PDT 24
Finished May 23 12:39:39 PM PDT 24
Peak memory 197832 kb
Host smart-0c9b1ffc-ce48-4b76-adf2-ec73e924103c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746268245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.3746268245
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.501771484
Short name T767
Test name
Test status
Simulation time 15233275 ps
CPU time 0.64 seconds
Started May 23 12:39:32 PM PDT 24
Finished May 23 12:39:34 PM PDT 24
Peak memory 196412 kb
Host smart-240f3876-9828-49ea-a252-fbb58d27decf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501771484 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.501771484
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.2407263070
Short name T90
Test name
Test status
Simulation time 50197797 ps
CPU time 0.62 seconds
Started May 23 12:39:42 PM PDT 24
Finished May 23 12:39:43 PM PDT 24
Peak memory 194704 kb
Host smart-dc3bae47-68b1-466b-aa2c-6c04abfa8ba0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407263070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.2407263070
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.2098260466
Short name T731
Test name
Test status
Simulation time 10305267 ps
CPU time 0.59 seconds
Started May 23 12:39:35 PM PDT 24
Finished May 23 12:39:37 PM PDT 24
Peak memory 193444 kb
Host smart-9a63a844-c743-467c-a16d-02515f060b7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098260466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.2098260466
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.434961512
Short name T836
Test name
Test status
Simulation time 12891418 ps
CPU time 0.66 seconds
Started May 23 12:39:35 PM PDT 24
Finished May 23 12:39:38 PM PDT 24
Peak memory 195496 kb
Host smart-f31ac47c-f78a-4ad7-92f7-7fc01d284b60
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434961512 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 11.gpio_same_csr_outstanding.434961512
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2503559328
Short name T829
Test name
Test status
Simulation time 453871624 ps
CPU time 2.46 seconds
Started May 23 12:39:42 PM PDT 24
Finished May 23 12:39:46 PM PDT 24
Peak memory 196812 kb
Host smart-891d61cd-faea-4893-b746-8c6046c6cb25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503559328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.2503559328
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.2238232311
Short name T47
Test name
Test status
Simulation time 253223282 ps
CPU time 1.16 seconds
Started May 23 12:39:33 PM PDT 24
Finished May 23 12:39:36 PM PDT 24
Peak memory 197880 kb
Host smart-9cf1adac-c5d4-445b-8938-94d5e57d870d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238232311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.2238232311
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.390682259
Short name T791
Test name
Test status
Simulation time 33938326 ps
CPU time 0.93 seconds
Started May 23 12:39:31 PM PDT 24
Finished May 23 12:39:33 PM PDT 24
Peak memory 197792 kb
Host smart-d48ba350-cef2-49bb-ae89-23343392aeb9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390682259 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.390682259
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.2963185688
Short name T789
Test name
Test status
Simulation time 64706880 ps
CPU time 0.58 seconds
Started May 23 12:39:35 PM PDT 24
Finished May 23 12:39:38 PM PDT 24
Peak memory 193144 kb
Host smart-185c5efe-7da8-4e8a-aa9f-b39dbf970a03
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963185688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.2963185688
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.1031649532
Short name T725
Test name
Test status
Simulation time 45610933 ps
CPU time 0.62 seconds
Started May 23 12:39:34 PM PDT 24
Finished May 23 12:39:36 PM PDT 24
Peak memory 194180 kb
Host smart-3453068a-3e97-4689-8346-e2d0f54ce05e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031649532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.1031649532
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.1061454704
Short name T105
Test name
Test status
Simulation time 58462768 ps
CPU time 0.88 seconds
Started May 23 12:39:34 PM PDT 24
Finished May 23 12:39:37 PM PDT 24
Peak memory 195976 kb
Host smart-06b8f65c-f2ca-4469-bab3-44d94d9bcec5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061454704 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.1061454704
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.3586499751
Short name T794
Test name
Test status
Simulation time 37006107 ps
CPU time 1.88 seconds
Started May 23 12:39:36 PM PDT 24
Finished May 23 12:39:40 PM PDT 24
Peak memory 197812 kb
Host smart-4b70ed3d-4103-44a8-b37d-ac359297980e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586499751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.3586499751
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1197900538
Short name T40
Test name
Test status
Simulation time 43507907 ps
CPU time 0.88 seconds
Started May 23 12:39:35 PM PDT 24
Finished May 23 12:39:38 PM PDT 24
Peak memory 197164 kb
Host smart-4d9c956c-0d72-4d2d-862f-6acad61455e2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197900538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.1197900538
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.2476511664
Short name T796
Test name
Test status
Simulation time 213050147 ps
CPU time 1.14 seconds
Started May 23 12:39:35 PM PDT 24
Finished May 23 12:39:39 PM PDT 24
Peak memory 197896 kb
Host smart-76104f2a-f288-4d30-a0c2-4dd0d7d7b964
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476511664 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.2476511664
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.772289439
Short name T716
Test name
Test status
Simulation time 36334766 ps
CPU time 0.58 seconds
Started May 23 12:39:37 PM PDT 24
Finished May 23 12:39:39 PM PDT 24
Peak memory 193488 kb
Host smart-2284aa8c-bd14-4b9f-9775-2dac971a411a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772289439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.772289439
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.2761175005
Short name T753
Test name
Test status
Simulation time 71717404 ps
CPU time 0.79 seconds
Started May 23 12:39:43 PM PDT 24
Finished May 23 12:39:45 PM PDT 24
Peak memory 195828 kb
Host smart-9c1bedf7-98ff-4e12-bf2f-1cffc0ea7fd1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761175005 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.2761175005
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.2604272539
Short name T775
Test name
Test status
Simulation time 34863414 ps
CPU time 1.8 seconds
Started May 23 12:39:32 PM PDT 24
Finished May 23 12:39:35 PM PDT 24
Peak memory 197792 kb
Host smart-21a32dfc-0a51-489b-9e2c-ab2697377695
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604272539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.2604272539
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.1526472891
Short name T39
Test name
Test status
Simulation time 527170212 ps
CPU time 1.37 seconds
Started May 23 12:39:31 PM PDT 24
Finished May 23 12:39:34 PM PDT 24
Peak memory 197816 kb
Host smart-456e63c3-f57b-4227-8489-dc239bd18d46
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526472891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.1526472891
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.4008415464
Short name T737
Test name
Test status
Simulation time 57583188 ps
CPU time 0.73 seconds
Started May 23 12:39:34 PM PDT 24
Finished May 23 12:39:37 PM PDT 24
Peak memory 197788 kb
Host smart-1467dbc2-34de-462a-af1a-739b0b3c3996
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008415464 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.4008415464
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.1621168101
Short name T728
Test name
Test status
Simulation time 36249462 ps
CPU time 0.6 seconds
Started May 23 12:39:32 PM PDT 24
Finished May 23 12:39:35 PM PDT 24
Peak memory 194516 kb
Host smart-9d15b12f-86a0-48df-9a51-9470e82bae85
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621168101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.1621168101
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.2753479300
Short name T758
Test name
Test status
Simulation time 46793412 ps
CPU time 0.61 seconds
Started May 23 12:39:35 PM PDT 24
Finished May 23 12:39:37 PM PDT 24
Peak memory 194256 kb
Host smart-b8513084-1762-47ee-a634-f7f212b25919
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753479300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.2753479300
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2273983881
Short name T99
Test name
Test status
Simulation time 44917862 ps
CPU time 0.73 seconds
Started May 23 12:39:36 PM PDT 24
Finished May 23 12:39:39 PM PDT 24
Peak memory 195588 kb
Host smart-edd6ad49-cd38-4eb7-a3cd-69245c575fa9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273983881 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.2273983881
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.4268496935
Short name T751
Test name
Test status
Simulation time 107270548 ps
CPU time 2.17 seconds
Started May 23 12:39:35 PM PDT 24
Finished May 23 12:39:40 PM PDT 24
Peak memory 197832 kb
Host smart-21169038-9071-49a1-a8a3-045a5d2c6675
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268496935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.4268496935
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1563359954
Short name T109
Test name
Test status
Simulation time 47623292 ps
CPU time 0.91 seconds
Started May 23 12:39:33 PM PDT 24
Finished May 23 12:39:36 PM PDT 24
Peak memory 197136 kb
Host smart-2ee83988-6900-4ab1-a803-9987f4453475
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563359954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.1563359954
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2540472937
Short name T771
Test name
Test status
Simulation time 36333611 ps
CPU time 1.57 seconds
Started May 23 12:39:34 PM PDT 24
Finished May 23 12:39:37 PM PDT 24
Peak memory 197948 kb
Host smart-014d62a7-ab56-4691-b845-c6a23aa5ba51
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540472937 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.2540472937
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.3363158307
Short name T806
Test name
Test status
Simulation time 32559320 ps
CPU time 0.58 seconds
Started May 23 12:39:35 PM PDT 24
Finished May 23 12:39:38 PM PDT 24
Peak memory 193100 kb
Host smart-6965c5d5-b386-418c-b9b1-3747f014a6f3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363158307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.3363158307
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.4102305905
Short name T819
Test name
Test status
Simulation time 14449746 ps
CPU time 0.57 seconds
Started May 23 12:39:43 PM PDT 24
Finished May 23 12:39:45 PM PDT 24
Peak memory 193436 kb
Host smart-75e58483-5fef-466c-b93c-3e15497d6266
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102305905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.4102305905
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.715366652
Short name T818
Test name
Test status
Simulation time 13513049 ps
CPU time 0.65 seconds
Started May 23 12:39:42 PM PDT 24
Finished May 23 12:39:44 PM PDT 24
Peak memory 193852 kb
Host smart-1f2b9cfb-0574-4f16-93f7-42c8df9cb069
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715366652 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 15.gpio_same_csr_outstanding.715366652
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.4133600946
Short name T773
Test name
Test status
Simulation time 422392654 ps
CPU time 2.26 seconds
Started May 23 12:39:45 PM PDT 24
Finished May 23 12:39:49 PM PDT 24
Peak memory 197820 kb
Host smart-d262670b-a211-44d6-8132-d1b180733837
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133600946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.4133600946
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2951324834
Short name T52
Test name
Test status
Simulation time 146905927 ps
CPU time 1.12 seconds
Started May 23 12:39:47 PM PDT 24
Finished May 23 12:39:51 PM PDT 24
Peak memory 197852 kb
Host smart-7d0a67c0-e7e1-476e-bc3e-f623decc2bb1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951324834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.2951324834
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.1995280210
Short name T724
Test name
Test status
Simulation time 36845492 ps
CPU time 0.73 seconds
Started May 23 12:39:49 PM PDT 24
Finished May 23 12:39:53 PM PDT 24
Peak memory 197752 kb
Host smart-f1729416-ecc8-49f2-bb38-a30d00931d0f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995280210 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.1995280210
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.991950382
Short name T89
Test name
Test status
Simulation time 45166093 ps
CPU time 0.61 seconds
Started May 23 12:39:48 PM PDT 24
Finished May 23 12:39:52 PM PDT 24
Peak memory 194316 kb
Host smart-1374984b-540a-4c2c-96e4-72922ba644c2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991950382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio
_csr_rw.991950382
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.2816317716
Short name T738
Test name
Test status
Simulation time 60777729 ps
CPU time 0.64 seconds
Started May 23 12:39:46 PM PDT 24
Finished May 23 12:39:49 PM PDT 24
Peak memory 193440 kb
Host smart-22c36814-fbdd-4661-9261-0e27d14fc885
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816317716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.2816317716
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1315410728
Short name T816
Test name
Test status
Simulation time 33861144 ps
CPU time 0.67 seconds
Started May 23 12:39:49 PM PDT 24
Finished May 23 12:39:53 PM PDT 24
Peak memory 194456 kb
Host smart-a0d8a72c-ec73-4736-a71a-d3a3e2803907
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315410728 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.1315410728
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.257584738
Short name T776
Test name
Test status
Simulation time 64543121 ps
CPU time 1.43 seconds
Started May 23 12:39:50 PM PDT 24
Finished May 23 12:39:54 PM PDT 24
Peak memory 197756 kb
Host smart-101509e0-da99-4a87-a9b4-7b579042983b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257584738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.257584738
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.2821336109
Short name T51
Test name
Test status
Simulation time 536176190 ps
CPU time 1.4 seconds
Started May 23 12:39:50 PM PDT 24
Finished May 23 12:39:54 PM PDT 24
Peak memory 197848 kb
Host smart-82a7818d-16fd-41db-b11a-92af9c40b232
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821336109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.2821336109
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2281761697
Short name T798
Test name
Test status
Simulation time 43177124 ps
CPU time 1.06 seconds
Started May 23 12:39:43 PM PDT 24
Finished May 23 12:39:45 PM PDT 24
Peak memory 197992 kb
Host smart-0d491b03-fc8f-4f35-8ea0-908426dfccd4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281761697 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.2281761697
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.567754333
Short name T780
Test name
Test status
Simulation time 13319875 ps
CPU time 0.58 seconds
Started May 23 12:39:45 PM PDT 24
Finished May 23 12:39:46 PM PDT 24
Peak memory 194416 kb
Host smart-163dd113-a371-4ac7-b740-1b6151d75766
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567754333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio
_csr_rw.567754333
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.3476348885
Short name T747
Test name
Test status
Simulation time 35764687 ps
CPU time 0.6 seconds
Started May 23 12:39:45 PM PDT 24
Finished May 23 12:39:47 PM PDT 24
Peak memory 193468 kb
Host smart-75891cc2-41f0-4e7f-bc0f-1ea6fc64529b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476348885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.3476348885
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3202160442
Short name T839
Test name
Test status
Simulation time 100750098 ps
CPU time 0.75 seconds
Started May 23 12:39:48 PM PDT 24
Finished May 23 12:39:52 PM PDT 24
Peak memory 195820 kb
Host smart-5d7f144e-447b-46f8-b085-ffdef5c3f2c9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202160442 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.3202160442
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.2615112589
Short name T779
Test name
Test status
Simulation time 43518219 ps
CPU time 1.3 seconds
Started May 23 12:39:48 PM PDT 24
Finished May 23 12:39:53 PM PDT 24
Peak memory 197816 kb
Host smart-e6c53dd6-c25e-48da-8485-f11495eb4d8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615112589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.2615112589
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1372242274
Short name T834
Test name
Test status
Simulation time 69854984 ps
CPU time 1.14 seconds
Started May 23 12:39:46 PM PDT 24
Finished May 23 12:39:50 PM PDT 24
Peak memory 197804 kb
Host smart-82ff6157-0bc2-486f-98bb-2475d2b90724
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372242274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.1372242274
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.1992888961
Short name T723
Test name
Test status
Simulation time 43374111 ps
CPU time 1.23 seconds
Started May 23 12:39:44 PM PDT 24
Finished May 23 12:39:47 PM PDT 24
Peak memory 197844 kb
Host smart-27ea9e65-278d-4e52-838d-bbd7a6c62034
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992888961 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.1992888961
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.945873830
Short name T750
Test name
Test status
Simulation time 22918704 ps
CPU time 0.61 seconds
Started May 23 12:39:43 PM PDT 24
Finished May 23 12:39:45 PM PDT 24
Peak memory 194644 kb
Host smart-103fa79e-5f74-463c-babe-a4cdb49246b2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945873830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio
_csr_rw.945873830
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.1744762418
Short name T828
Test name
Test status
Simulation time 83809209 ps
CPU time 0.64 seconds
Started May 23 12:39:50 PM PDT 24
Finished May 23 12:39:53 PM PDT 24
Peak memory 193288 kb
Host smart-a1201642-1963-41b0-b062-c7be7baa2f2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744762418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.1744762418
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.3309662038
Short name T98
Test name
Test status
Simulation time 19148713 ps
CPU time 0.89 seconds
Started May 23 12:39:47 PM PDT 24
Finished May 23 12:39:51 PM PDT 24
Peak memory 197632 kb
Host smart-70c8ca66-d3af-45a1-a9f3-dec0e8623689
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309662038 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.3309662038
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.2694255835
Short name T777
Test name
Test status
Simulation time 202530934 ps
CPU time 2.35 seconds
Started May 23 12:39:47 PM PDT 24
Finished May 23 12:39:52 PM PDT 24
Peak memory 197816 kb
Host smart-03630b62-25f8-4e70-a75f-0c360f0050cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694255835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.2694255835
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.167061091
Short name T788
Test name
Test status
Simulation time 264544297 ps
CPU time 1.09 seconds
Started May 23 12:39:46 PM PDT 24
Finished May 23 12:39:49 PM PDT 24
Peak memory 197316 kb
Host smart-e42dc6fd-2e05-490d-bf0a-20525f795cd0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167061091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 18.gpio_tl_intg_err.167061091
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.2617118344
Short name T770
Test name
Test status
Simulation time 16281470 ps
CPU time 0.65 seconds
Started May 23 12:39:49 PM PDT 24
Finished May 23 12:39:53 PM PDT 24
Peak memory 197480 kb
Host smart-41f42bfb-ea18-4f7a-affe-bac0391a945a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617118344 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.2617118344
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.2438834549
Short name T769
Test name
Test status
Simulation time 53037430 ps
CPU time 0.61 seconds
Started May 23 12:39:46 PM PDT 24
Finished May 23 12:39:48 PM PDT 24
Peak memory 194620 kb
Host smart-3d78a134-da53-4dfe-bb9b-4a8d8d67fd2f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438834549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.2438834549
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.1160375082
Short name T721
Test name
Test status
Simulation time 43943152 ps
CPU time 0.61 seconds
Started May 23 12:40:02 PM PDT 24
Finished May 23 12:40:07 PM PDT 24
Peak memory 193564 kb
Host smart-53fb177c-2bfe-4919-b6b8-f3e4b9a5f139
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160375082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.1160375082
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3625074808
Short name T833
Test name
Test status
Simulation time 13520300 ps
CPU time 0.66 seconds
Started May 23 12:39:45 PM PDT 24
Finished May 23 12:39:47 PM PDT 24
Peak memory 194684 kb
Host smart-b79a44fc-e029-47bc-897c-7d4bac3ce782
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625074808 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.3625074808
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3395390201
Short name T784
Test name
Test status
Simulation time 95813772 ps
CPU time 1.77 seconds
Started May 23 12:40:02 PM PDT 24
Finished May 23 12:40:07 PM PDT 24
Peak memory 197888 kb
Host smart-b0b8e634-69c6-4855-8cf4-3de223e3e385
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395390201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.3395390201
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.2371339047
Short name T54
Test name
Test status
Simulation time 462414245 ps
CPU time 1.48 seconds
Started May 23 12:39:49 PM PDT 24
Finished May 23 12:39:53 PM PDT 24
Peak memory 197836 kb
Host smart-c6b56dc3-d6db-4772-a9ac-7fef5ca498db
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371339047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.2371339047
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.1317404092
Short name T735
Test name
Test status
Simulation time 52103925 ps
CPU time 0.71 seconds
Started May 23 12:39:11 PM PDT 24
Finished May 23 12:39:14 PM PDT 24
Peak memory 195128 kb
Host smart-3fe62775-b64c-4406-b2b4-2b9d74139164
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317404092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.1317404092
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.1017201812
Short name T86
Test name
Test status
Simulation time 60934853 ps
CPU time 2.18 seconds
Started May 23 12:39:05 PM PDT 24
Finished May 23 12:39:08 PM PDT 24
Peak memory 196812 kb
Host smart-b3a0bcfc-9840-4b04-9350-630db5bdce83
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017201812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.1017201812
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1709010441
Short name T107
Test name
Test status
Simulation time 92719320 ps
CPU time 0.63 seconds
Started May 23 12:39:06 PM PDT 24
Finished May 23 12:39:08 PM PDT 24
Peak memory 194324 kb
Host smart-704191e9-f43c-402f-8a9c-3288da1365ac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709010441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.1709010441
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.3903891381
Short name T781
Test name
Test status
Simulation time 28194589 ps
CPU time 1.17 seconds
Started May 23 12:39:07 PM PDT 24
Finished May 23 12:39:10 PM PDT 24
Peak memory 197888 kb
Host smart-9a39e445-de4d-4637-8593-a0094ad9274e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903891381 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.3903891381
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.3580520745
Short name T87
Test name
Test status
Simulation time 15826674 ps
CPU time 0.6 seconds
Started May 23 12:39:07 PM PDT 24
Finished May 23 12:39:09 PM PDT 24
Peak memory 194544 kb
Host smart-9b4ffb64-164e-4fd9-b536-eb75d3bd6060
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580520745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.3580520745
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.2027615974
Short name T743
Test name
Test status
Simulation time 17668676 ps
CPU time 0.59 seconds
Started May 23 12:39:08 PM PDT 24
Finished May 23 12:39:10 PM PDT 24
Peak memory 193552 kb
Host smart-fe976782-3b67-4564-8f0f-0c750e990bce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027615974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.2027615974
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.1225045147
Short name T103
Test name
Test status
Simulation time 21563134 ps
CPU time 0.85 seconds
Started May 23 12:39:06 PM PDT 24
Finished May 23 12:39:09 PM PDT 24
Peak memory 196972 kb
Host smart-0b0ff84a-c021-440f-9325-ca58fdad1940
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225045147 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.1225045147
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1528307642
Short name T785
Test name
Test status
Simulation time 170630331 ps
CPU time 2.53 seconds
Started May 23 12:39:06 PM PDT 24
Finished May 23 12:39:10 PM PDT 24
Peak memory 197840 kb
Host smart-cb963df3-aa89-4e46-b262-74b78770455d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528307642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.1528307642
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.1920797599
Short name T801
Test name
Test status
Simulation time 168936817 ps
CPU time 1.2 seconds
Started May 23 12:39:08 PM PDT 24
Finished May 23 12:39:11 PM PDT 24
Peak memory 197848 kb
Host smart-978ee61d-959f-46ba-a4d3-3cc28db04a79
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920797599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.1920797599
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.841122279
Short name T715
Test name
Test status
Simulation time 25342015 ps
CPU time 0.59 seconds
Started May 23 12:40:02 PM PDT 24
Finished May 23 12:40:07 PM PDT 24
Peak memory 193448 kb
Host smart-4586655f-afc9-4072-b83c-cdd1b6380212
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841122279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.841122279
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.1723584464
Short name T712
Test name
Test status
Simulation time 16274637 ps
CPU time 0.61 seconds
Started May 23 12:40:01 PM PDT 24
Finished May 23 12:40:04 PM PDT 24
Peak memory 193524 kb
Host smart-19463252-85ed-40a6-9eaf-bbbe35fd9d62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723584464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.1723584464
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.3432851874
Short name T756
Test name
Test status
Simulation time 35863805 ps
CPU time 0.59 seconds
Started May 23 12:40:02 PM PDT 24
Finished May 23 12:40:07 PM PDT 24
Peak memory 193412 kb
Host smart-dedb320a-0577-4cb2-8252-7bf85f618c53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432851874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.3432851874
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.1098216904
Short name T810
Test name
Test status
Simulation time 32860228 ps
CPU time 0.6 seconds
Started May 23 12:40:02 PM PDT 24
Finished May 23 12:40:07 PM PDT 24
Peak memory 193460 kb
Host smart-3841df71-c403-4314-8674-38ef14334586
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098216904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.1098216904
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.1113103994
Short name T722
Test name
Test status
Simulation time 31413036 ps
CPU time 0.61 seconds
Started May 23 12:40:01 PM PDT 24
Finished May 23 12:40:04 PM PDT 24
Peak memory 193436 kb
Host smart-7b82ef90-c2d5-476f-9689-ef9b3a84636d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113103994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.1113103994
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.2283888416
Short name T807
Test name
Test status
Simulation time 53933196 ps
CPU time 0.61 seconds
Started May 23 12:40:01 PM PDT 24
Finished May 23 12:40:03 PM PDT 24
Peak memory 193436 kb
Host smart-44051a34-db07-4fbc-911b-799f1660df34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283888416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.2283888416
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.15203281
Short name T768
Test name
Test status
Simulation time 36019975 ps
CPU time 0.58 seconds
Started May 23 12:40:01 PM PDT 24
Finished May 23 12:40:05 PM PDT 24
Peak memory 193576 kb
Host smart-9fa944fc-a9ac-44b9-8253-3c735b62144f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15203281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.15203281
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.4237108582
Short name T745
Test name
Test status
Simulation time 71976133 ps
CPU time 0.57 seconds
Started May 23 12:40:02 PM PDT 24
Finished May 23 12:40:07 PM PDT 24
Peak memory 194052 kb
Host smart-f936bfa1-eab8-465b-887f-f2aa64d3b9bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237108582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.4237108582
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.3697017780
Short name T713
Test name
Test status
Simulation time 14836001 ps
CPU time 0.62 seconds
Started May 23 12:40:00 PM PDT 24
Finished May 23 12:40:03 PM PDT 24
Peak memory 194220 kb
Host smart-5d0cead7-d267-49bc-ab48-82cb4a796fd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697017780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.3697017780
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.26264425
Short name T790
Test name
Test status
Simulation time 48860679 ps
CPU time 0.67 seconds
Started May 23 12:40:04 PM PDT 24
Finished May 23 12:40:08 PM PDT 24
Peak memory 194188 kb
Host smart-4d797c8a-d796-4063-bf9b-fa8102abce9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26264425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.26264425
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.3013315926
Short name T96
Test name
Test status
Simulation time 15695698 ps
CPU time 0.64 seconds
Started May 23 12:39:15 PM PDT 24
Finished May 23 12:39:17 PM PDT 24
Peak memory 194912 kb
Host smart-36cbe0f6-1691-4e92-8b8e-24b3a6ae50a3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013315926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.3013315926
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1446016603
Short name T772
Test name
Test status
Simulation time 899646079 ps
CPU time 2.57 seconds
Started May 23 12:39:09 PM PDT 24
Finished May 23 12:39:14 PM PDT 24
Peak memory 197756 kb
Host smart-9ed4759d-2f57-4607-9022-0674292b5b02
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446016603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.1446016603
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3639219300
Short name T821
Test name
Test status
Simulation time 15671789 ps
CPU time 0.63 seconds
Started May 23 12:39:09 PM PDT 24
Finished May 23 12:39:13 PM PDT 24
Peak memory 194132 kb
Host smart-0b484878-a0d2-48b7-98c4-1648d18eebdd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639219300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.3639219300
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3794674825
Short name T804
Test name
Test status
Simulation time 57008138 ps
CPU time 0.67 seconds
Started May 23 12:39:08 PM PDT 24
Finished May 23 12:39:12 PM PDT 24
Peak memory 196592 kb
Host smart-f8b40b29-ce72-4da9-8be4-f1f5454d154a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794674825 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.3794674825
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1141418511
Short name T727
Test name
Test status
Simulation time 15496063 ps
CPU time 0.61 seconds
Started May 23 12:39:06 PM PDT 24
Finished May 23 12:39:09 PM PDT 24
Peak memory 195192 kb
Host smart-353e33d9-5073-4145-92ee-041f843a78fb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141418511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.1141418511
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.4289104893
Short name T782
Test name
Test status
Simulation time 45485163 ps
CPU time 0.56 seconds
Started May 23 12:39:08 PM PDT 24
Finished May 23 12:39:11 PM PDT 24
Peak memory 193512 kb
Host smart-f4a9c9d7-40c6-4b77-8125-d817f9f1d357
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289104893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.4289104893
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3716950532
Short name T102
Test name
Test status
Simulation time 30240123 ps
CPU time 0.8 seconds
Started May 23 12:39:09 PM PDT 24
Finished May 23 12:39:12 PM PDT 24
Peak memory 196020 kb
Host smart-aacbd8e8-000d-42ee-8ce8-f1250a80716b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716950532 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.3716950532
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.1779482590
Short name T795
Test name
Test status
Simulation time 439010687 ps
CPU time 2.06 seconds
Started May 23 12:39:09 PM PDT 24
Finished May 23 12:39:14 PM PDT 24
Peak memory 197880 kb
Host smart-f83fcec4-5942-434c-b1fe-fda03ee3f760
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779482590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.1779482590
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.956033462
Short name T50
Test name
Test status
Simulation time 165613305 ps
CPU time 0.86 seconds
Started May 23 12:39:09 PM PDT 24
Finished May 23 12:39:12 PM PDT 24
Peak memory 196912 kb
Host smart-ccea2ea6-9d47-4ab3-a4c0-f54a23e0cdb7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956033462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.gpio_tl_intg_err.956033462
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.1777625981
Short name T815
Test name
Test status
Simulation time 104107030 ps
CPU time 0.63 seconds
Started May 23 12:40:03 PM PDT 24
Finished May 23 12:40:08 PM PDT 24
Peak memory 193472 kb
Host smart-88bf44a0-e192-4738-a4f9-39c1de58e151
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777625981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.1777625981
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.2173929166
Short name T757
Test name
Test status
Simulation time 51953193 ps
CPU time 0.61 seconds
Started May 23 12:40:02 PM PDT 24
Finished May 23 12:40:06 PM PDT 24
Peak memory 193480 kb
Host smart-17926aba-8c0c-4c8d-8799-8f40c4c27c4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173929166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.2173929166
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.420532470
Short name T802
Test name
Test status
Simulation time 18348096 ps
CPU time 0.61 seconds
Started May 23 12:40:02 PM PDT 24
Finished May 23 12:40:06 PM PDT 24
Peak memory 193588 kb
Host smart-8811315f-5fc4-4fa8-a5a1-d96540f5fe4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420532470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.420532470
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.170936920
Short name T835
Test name
Test status
Simulation time 20309469 ps
CPU time 0.64 seconds
Started May 23 12:40:00 PM PDT 24
Finished May 23 12:40:03 PM PDT 24
Peak memory 193548 kb
Host smart-62c92d85-1337-4195-849e-28c2b5bff55d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170936920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.170936920
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.317442484
Short name T840
Test name
Test status
Simulation time 48922514 ps
CPU time 0.61 seconds
Started May 23 12:40:00 PM PDT 24
Finished May 23 12:40:03 PM PDT 24
Peak memory 193700 kb
Host smart-6796b133-37f4-400f-9f2b-b229a5c3e4d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317442484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.317442484
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.2619604656
Short name T734
Test name
Test status
Simulation time 53702911 ps
CPU time 0.6 seconds
Started May 23 12:40:02 PM PDT 24
Finished May 23 12:40:07 PM PDT 24
Peak memory 194096 kb
Host smart-04cf490c-88ea-46f6-82eb-8d175f955948
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619604656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.2619604656
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.850169124
Short name T783
Test name
Test status
Simulation time 64432938 ps
CPU time 0.6 seconds
Started May 23 12:40:01 PM PDT 24
Finished May 23 12:40:04 PM PDT 24
Peak memory 193512 kb
Host smart-4dfca0e5-37a8-471e-8ea3-3453c2589d51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850169124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.850169124
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.2000047302
Short name T744
Test name
Test status
Simulation time 33178397 ps
CPU time 0.61 seconds
Started May 23 12:40:03 PM PDT 24
Finished May 23 12:40:07 PM PDT 24
Peak memory 193580 kb
Host smart-92d98800-fabf-47fe-81d4-8d6f3e721788
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000047302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.2000047302
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.2915104146
Short name T825
Test name
Test status
Simulation time 21384049 ps
CPU time 0.6 seconds
Started May 23 12:40:05 PM PDT 24
Finished May 23 12:40:09 PM PDT 24
Peak memory 193484 kb
Host smart-f9472072-0ed3-43e6-a1f3-3bd3026fae63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915104146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.2915104146
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.3802932457
Short name T797
Test name
Test status
Simulation time 39514784 ps
CPU time 0.61 seconds
Started May 23 12:40:03 PM PDT 24
Finished May 23 12:40:08 PM PDT 24
Peak memory 193468 kb
Host smart-ff8dbd73-9716-4012-ab9c-d874db273794
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802932457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.3802932457
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.1412886538
Short name T97
Test name
Test status
Simulation time 42905086 ps
CPU time 0.83 seconds
Started May 23 12:39:15 PM PDT 24
Finished May 23 12:39:17 PM PDT 24
Peak memory 195424 kb
Host smart-194f4cbf-e771-429d-9e00-bc9fde0e1a91
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412886538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.1412886538
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.1935016174
Short name T746
Test name
Test status
Simulation time 351337410 ps
CPU time 3.22 seconds
Started May 23 12:39:13 PM PDT 24
Finished May 23 12:39:17 PM PDT 24
Peak memory 197152 kb
Host smart-60fd1a4f-b87b-4c2d-94f5-5e22e62446e4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935016174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.1935016174
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.897218590
Short name T809
Test name
Test status
Simulation time 248254526 ps
CPU time 0.65 seconds
Started May 23 12:39:11 PM PDT 24
Finished May 23 12:39:14 PM PDT 24
Peak memory 194736 kb
Host smart-fc66693c-cc69-46a4-b8c0-75a95fceeda8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897218590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.897218590
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.257476704
Short name T759
Test name
Test status
Simulation time 78049710 ps
CPU time 1.78 seconds
Started May 23 12:39:07 PM PDT 24
Finished May 23 12:39:11 PM PDT 24
Peak memory 197872 kb
Host smart-3f576307-3a7e-4d05-a144-796ecf8965ed
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257476704 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.257476704
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.333699337
Short name T93
Test name
Test status
Simulation time 90715806 ps
CPU time 0.59 seconds
Started May 23 12:39:06 PM PDT 24
Finished May 23 12:39:09 PM PDT 24
Peak memory 194700 kb
Host smart-a5226917-08fb-49cf-b8d7-9c66b1503d5b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333699337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_
csr_rw.333699337
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.3683928412
Short name T763
Test name
Test status
Simulation time 17090530 ps
CPU time 0.57 seconds
Started May 23 12:39:10 PM PDT 24
Finished May 23 12:39:13 PM PDT 24
Peak memory 193564 kb
Host smart-a03ce77a-5373-43c8-84c6-179b4a9ef5de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683928412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.3683928412
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.1193980659
Short name T101
Test name
Test status
Simulation time 293801564 ps
CPU time 0.74 seconds
Started May 23 12:39:08 PM PDT 24
Finished May 23 12:39:12 PM PDT 24
Peak memory 195952 kb
Host smart-4f0c2c19-1c17-4c42-9679-8a35d4e00d21
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193980659 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.1193980659
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.2179808589
Short name T822
Test name
Test status
Simulation time 219395695 ps
CPU time 1.97 seconds
Started May 23 12:39:10 PM PDT 24
Finished May 23 12:39:14 PM PDT 24
Peak memory 197908 kb
Host smart-457b338e-9b0f-48b0-9de1-901396c758ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179808589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.2179808589
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2300611579
Short name T764
Test name
Test status
Simulation time 47143364 ps
CPU time 0.87 seconds
Started May 23 12:39:10 PM PDT 24
Finished May 23 12:39:13 PM PDT 24
Peak memory 197196 kb
Host smart-493771a6-60ac-4199-a708-ea25d4fdcd53
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300611579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.2300611579
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.3250427185
Short name T755
Test name
Test status
Simulation time 32570046 ps
CPU time 0.67 seconds
Started May 23 12:40:00 PM PDT 24
Finished May 23 12:40:03 PM PDT 24
Peak memory 194152 kb
Host smart-4d21117c-0240-4959-8363-2c92980d7538
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250427185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.3250427185
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.3490292066
Short name T820
Test name
Test status
Simulation time 87627919 ps
CPU time 0.58 seconds
Started May 23 12:40:03 PM PDT 24
Finished May 23 12:40:08 PM PDT 24
Peak memory 193472 kb
Host smart-41052cfe-212b-492d-9fbd-b8205ff1e4c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490292066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.3490292066
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.304784253
Short name T837
Test name
Test status
Simulation time 29541941 ps
CPU time 0.59 seconds
Started May 23 12:40:02 PM PDT 24
Finished May 23 12:40:07 PM PDT 24
Peak memory 194260 kb
Host smart-65b45df2-664d-4e18-b870-85b66b5d2ce8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304784253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.304784253
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.4191291233
Short name T823
Test name
Test status
Simulation time 18601061 ps
CPU time 0.62 seconds
Started May 23 12:40:00 PM PDT 24
Finished May 23 12:40:03 PM PDT 24
Peak memory 193460 kb
Host smart-164f61bb-f19d-4839-9395-21836ed552d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191291233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.4191291233
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.2341327724
Short name T824
Test name
Test status
Simulation time 43479148 ps
CPU time 0.6 seconds
Started May 23 12:40:04 PM PDT 24
Finished May 23 12:40:09 PM PDT 24
Peak memory 193516 kb
Host smart-46f30654-84b1-4d45-b48f-1f838722fcc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341327724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.2341327724
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.738605379
Short name T741
Test name
Test status
Simulation time 43502542 ps
CPU time 0.61 seconds
Started May 23 12:40:02 PM PDT 24
Finished May 23 12:40:06 PM PDT 24
Peak memory 193484 kb
Host smart-96db38e9-587e-4619-83d9-ca9f925c9c6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738605379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.738605379
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.593500122
Short name T832
Test name
Test status
Simulation time 12387961 ps
CPU time 0.59 seconds
Started May 23 12:40:03 PM PDT 24
Finished May 23 12:40:07 PM PDT 24
Peak memory 193468 kb
Host smart-a56243e1-b1d7-4674-991a-9066bd3ad7f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593500122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.593500122
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.543692502
Short name T720
Test name
Test status
Simulation time 19581115 ps
CPU time 0.63 seconds
Started May 23 12:40:03 PM PDT 24
Finished May 23 12:40:08 PM PDT 24
Peak memory 193488 kb
Host smart-a536ad5c-1040-4c68-8a37-84aa93e29eb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543692502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.543692502
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.1115634462
Short name T729
Test name
Test status
Simulation time 11314817 ps
CPU time 0.63 seconds
Started May 23 12:40:03 PM PDT 24
Finished May 23 12:40:08 PM PDT 24
Peak memory 193472 kb
Host smart-ce95e9dc-1763-4b87-a562-f87a4f1f47ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115634462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.1115634462
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.1440973180
Short name T732
Test name
Test status
Simulation time 45860659 ps
CPU time 0.58 seconds
Started May 23 12:40:01 PM PDT 24
Finished May 23 12:40:04 PM PDT 24
Peak memory 193472 kb
Host smart-66cc2bf4-52cf-459b-ae61-25b792eb2e1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440973180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.1440973180
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1797202885
Short name T793
Test name
Test status
Simulation time 21657976 ps
CPU time 0.71 seconds
Started May 23 12:39:20 PM PDT 24
Finished May 23 12:39:22 PM PDT 24
Peak memory 197636 kb
Host smart-1ab07bf6-477e-49d6-a329-e0c52b9f02fa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797202885 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.1797202885
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.3134463024
Short name T108
Test name
Test status
Simulation time 52907411 ps
CPU time 0.65 seconds
Started May 23 12:39:11 PM PDT 24
Finished May 23 12:39:14 PM PDT 24
Peak memory 194548 kb
Host smart-33e19dbc-eb31-43a5-9189-0584d5669899
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134463024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.3134463024
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.2201823809
Short name T805
Test name
Test status
Simulation time 46359524 ps
CPU time 0.61 seconds
Started May 23 12:39:22 PM PDT 24
Finished May 23 12:39:25 PM PDT 24
Peak memory 194272 kb
Host smart-45aeaed3-c225-41ff-badb-7ac73895dc63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201823809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.2201823809
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.456826657
Short name T817
Test name
Test status
Simulation time 30301313 ps
CPU time 0.77 seconds
Started May 23 12:39:22 PM PDT 24
Finished May 23 12:39:25 PM PDT 24
Peak memory 196148 kb
Host smart-b91b77fa-7501-4623-a7aa-ef1f6a368972
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456826657 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 5.gpio_same_csr_outstanding.456826657
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.233492947
Short name T719
Test name
Test status
Simulation time 22961623 ps
CPU time 1.21 seconds
Started May 23 12:39:21 PM PDT 24
Finished May 23 12:39:24 PM PDT 24
Peak memory 197844 kb
Host smart-3cbedccc-2fd5-4c97-9a09-81c620255e1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233492947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.233492947
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2312642176
Short name T766
Test name
Test status
Simulation time 113321883 ps
CPU time 0.86 seconds
Started May 23 12:39:21 PM PDT 24
Finished May 23 12:39:23 PM PDT 24
Peak memory 197820 kb
Host smart-67875605-51b1-4a2f-ac40-368ecfc31226
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312642176 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.2312642176
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1051905460
Short name T733
Test name
Test status
Simulation time 19339197 ps
CPU time 0.64 seconds
Started May 23 12:39:19 PM PDT 24
Finished May 23 12:39:21 PM PDT 24
Peak memory 193808 kb
Host smart-c13302f4-86bd-4f00-b0a9-b6887f376a82
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051905460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.1051905460
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.1064465101
Short name T813
Test name
Test status
Simulation time 41635365 ps
CPU time 0.62 seconds
Started May 23 12:39:19 PM PDT 24
Finished May 23 12:39:21 PM PDT 24
Peak memory 193560 kb
Host smart-808b8190-383c-4da7-8993-744ca2abd549
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064465101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.1064465101
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.1109775123
Short name T749
Test name
Test status
Simulation time 30644729 ps
CPU time 0.76 seconds
Started May 23 12:39:23 PM PDT 24
Finished May 23 12:39:26 PM PDT 24
Peak memory 196000 kb
Host smart-d3d35c6d-acf8-468e-8820-7d5e13257360
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109775123 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.1109775123
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.3848656513
Short name T827
Test name
Test status
Simulation time 480315022 ps
CPU time 2.27 seconds
Started May 23 12:39:18 PM PDT 24
Finished May 23 12:39:21 PM PDT 24
Peak memory 197820 kb
Host smart-acdd17a4-ef79-45d3-bc8b-6a04f161f6f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848656513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.3848656513
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.802135141
Short name T48
Test name
Test status
Simulation time 250968302 ps
CPU time 1.17 seconds
Started May 23 12:39:20 PM PDT 24
Finished May 23 12:39:22 PM PDT 24
Peak memory 197808 kb
Host smart-876ff72c-a5ce-42aa-bd10-2d6630b225ed
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802135141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 6.gpio_tl_intg_err.802135141
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.1069831002
Short name T826
Test name
Test status
Simulation time 39423698 ps
CPU time 1.1 seconds
Started May 23 12:39:20 PM PDT 24
Finished May 23 12:39:23 PM PDT 24
Peak memory 197812 kb
Host smart-ed594856-c413-48af-9ef3-5ded170676a9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069831002 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.1069831002
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.610650738
Short name T800
Test name
Test status
Simulation time 30641232 ps
CPU time 0.63 seconds
Started May 23 12:39:19 PM PDT 24
Finished May 23 12:39:21 PM PDT 24
Peak memory 194604 kb
Host smart-4d5987b1-8941-41f6-aac6-307fb823056f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610650738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_
csr_rw.610650738
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.170309181
Short name T787
Test name
Test status
Simulation time 18509210 ps
CPU time 0.61 seconds
Started May 23 12:39:23 PM PDT 24
Finished May 23 12:39:25 PM PDT 24
Peak memory 193520 kb
Host smart-31dec788-e21d-4ece-864f-e11cae9e402d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170309181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.170309181
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1276501984
Short name T774
Test name
Test status
Simulation time 22780997 ps
CPU time 0.75 seconds
Started May 23 12:39:18 PM PDT 24
Finished May 23 12:39:20 PM PDT 24
Peak memory 196664 kb
Host smart-3b26e78f-576e-43b5-8a7d-901bc95ce527
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276501984 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.1276501984
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.1998673513
Short name T714
Test name
Test status
Simulation time 39071645 ps
CPU time 1.98 seconds
Started May 23 12:39:22 PM PDT 24
Finished May 23 12:39:26 PM PDT 24
Peak memory 197868 kb
Host smart-4787d1e4-39bf-401b-81d9-f35baa647c21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998673513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.1998673513
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.1675747826
Short name T762
Test name
Test status
Simulation time 253271273 ps
CPU time 1.15 seconds
Started May 23 12:39:19 PM PDT 24
Finished May 23 12:39:21 PM PDT 24
Peak memory 197804 kb
Host smart-d4f1d944-f5b4-41d8-9e8e-b0678ccb1206
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675747826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.1675747826
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.2583019073
Short name T803
Test name
Test status
Simulation time 31934530 ps
CPU time 0.94 seconds
Started May 23 12:39:20 PM PDT 24
Finished May 23 12:39:22 PM PDT 24
Peak memory 197796 kb
Host smart-b44daa71-cfd9-4e26-9e1c-46b93d6530be
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583019073 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.2583019073
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3089203809
Short name T765
Test name
Test status
Simulation time 24595427 ps
CPU time 0.63 seconds
Started May 23 12:39:21 PM PDT 24
Finished May 23 12:39:23 PM PDT 24
Peak memory 195180 kb
Host smart-a576fd0a-d3e6-448c-8032-504d1358ad65
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089203809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.3089203809
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.537817740
Short name T717
Test name
Test status
Simulation time 14910256 ps
CPU time 0.63 seconds
Started May 23 12:39:22 PM PDT 24
Finished May 23 12:39:25 PM PDT 24
Peak memory 193624 kb
Host smart-82505e62-1c0b-4094-9a96-39230ea4c810
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537817740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.537817740
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.4172191295
Short name T88
Test name
Test status
Simulation time 20010368 ps
CPU time 0.74 seconds
Started May 23 12:39:19 PM PDT 24
Finished May 23 12:39:20 PM PDT 24
Peak memory 195112 kb
Host smart-c849d60d-f332-4f13-8ba9-939b2e95dbba
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172191295 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.4172191295
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2711800634
Short name T740
Test name
Test status
Simulation time 408042753 ps
CPU time 1.79 seconds
Started May 23 12:39:20 PM PDT 24
Finished May 23 12:39:23 PM PDT 24
Peak memory 197820 kb
Host smart-54db683b-3679-495d-95dd-09b0ab9ded91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711800634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.2711800634
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3025471040
Short name T730
Test name
Test status
Simulation time 28803872 ps
CPU time 1.27 seconds
Started May 23 12:39:25 PM PDT 24
Finished May 23 12:39:27 PM PDT 24
Peak memory 197936 kb
Host smart-3c3f9b90-408e-4009-8689-6b0a4c2b50a3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025471040 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.3025471040
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.295249115
Short name T726
Test name
Test status
Simulation time 12098715 ps
CPU time 0.58 seconds
Started May 23 12:39:19 PM PDT 24
Finished May 23 12:39:20 PM PDT 24
Peak memory 194468 kb
Host smart-972e3f3e-4f5f-4313-84d8-12c713978732
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295249115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_
csr_rw.295249115
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.1800476372
Short name T736
Test name
Test status
Simulation time 40832604 ps
CPU time 0.6 seconds
Started May 23 12:39:22 PM PDT 24
Finished May 23 12:39:24 PM PDT 24
Peak memory 194260 kb
Host smart-f9208a9b-aa69-4373-916c-c9ebddaffbe5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800476372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.1800476372
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.3287014656
Short name T100
Test name
Test status
Simulation time 42384861 ps
CPU time 0.98 seconds
Started May 23 12:39:25 PM PDT 24
Finished May 23 12:39:27 PM PDT 24
Peak memory 196188 kb
Host smart-b0fe004c-6253-4a27-be2d-ffc307ac984a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287014656 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.3287014656
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.3227439943
Short name T830
Test name
Test status
Simulation time 79442387 ps
CPU time 1.76 seconds
Started May 23 12:39:18 PM PDT 24
Finished May 23 12:39:21 PM PDT 24
Peak memory 197828 kb
Host smart-2c8ec5e4-da0c-457f-a5e0-17714446e769
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227439943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.3227439943
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.3084964216
Short name T792
Test name
Test status
Simulation time 108665639 ps
CPU time 1.48 seconds
Started May 23 12:39:27 PM PDT 24
Finished May 23 12:39:29 PM PDT 24
Peak memory 197900 kb
Host smart-9cf72600-afce-4fb7-a7a8-55ca66be84a8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084964216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.3084964216
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.1605608499
Short name T293
Test name
Test status
Simulation time 12145148 ps
CPU time 0.55 seconds
Started May 23 12:41:47 PM PDT 24
Finished May 23 12:41:48 PM PDT 24
Peak memory 193812 kb
Host smart-02309de4-6f21-474c-aa97-0c721096a388
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605608499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.1605608499
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.680405961
Short name T228
Test name
Test status
Simulation time 47890974 ps
CPU time 0.88 seconds
Started May 23 12:41:39 PM PDT 24
Finished May 23 12:41:41 PM PDT 24
Peak memory 195756 kb
Host smart-8d1c3f4d-ec8e-4297-bffb-668564b56ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680405961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.680405961
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.4130080179
Short name T369
Test name
Test status
Simulation time 372428010 ps
CPU time 12.33 seconds
Started May 23 12:41:47 PM PDT 24
Finished May 23 12:42:00 PM PDT 24
Peak memory 196364 kb
Host smart-e9144f0d-16e8-4a4a-89b1-492ab3e8731e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130080179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.4130080179
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.1835577516
Short name T316
Test name
Test status
Simulation time 68263176 ps
CPU time 0.84 seconds
Started May 23 12:41:46 PM PDT 24
Finished May 23 12:41:48 PM PDT 24
Peak memory 195556 kb
Host smart-97c4bae4-05e2-49da-b05a-47a75873da52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835577516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.1835577516
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.1603721418
Short name T368
Test name
Test status
Simulation time 103884818 ps
CPU time 0.86 seconds
Started May 23 12:41:36 PM PDT 24
Finished May 23 12:41:38 PM PDT 24
Peak memory 196776 kb
Host smart-6806e2df-4912-4a7f-987f-d5464fb77ffe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603721418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.1603721418
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.3776868595
Short name T384
Test name
Test status
Simulation time 137416461 ps
CPU time 1.73 seconds
Started May 23 12:41:39 PM PDT 24
Finished May 23 12:41:42 PM PDT 24
Peak memory 197884 kb
Host smart-3ac58e75-00b5-411c-93ca-6886132f6921
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776868595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.3776868595
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.1973719388
Short name T135
Test name
Test status
Simulation time 135574961 ps
CPU time 2.24 seconds
Started May 23 12:41:36 PM PDT 24
Finished May 23 12:41:40 PM PDT 24
Peak memory 196948 kb
Host smart-96397d9a-ffc8-4ac7-a4a2-b33f88e5468c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973719388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
1973719388
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.2299620087
Short name T302
Test name
Test status
Simulation time 48823845 ps
CPU time 0.91 seconds
Started May 23 12:41:39 PM PDT 24
Finished May 23 12:41:42 PM PDT 24
Peak memory 195708 kb
Host smart-b57188db-2be0-4fd5-bcce-ed19862f7d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299620087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.2299620087
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.665503085
Short name T703
Test name
Test status
Simulation time 42499888 ps
CPU time 0.96 seconds
Started May 23 12:41:39 PM PDT 24
Finished May 23 12:41:41 PM PDT 24
Peak memory 195668 kb
Host smart-c3fdaf58-f9cf-41af-bd4e-dd6456d8ec96
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665503085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup_
pulldown.665503085
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.2503641028
Short name T198
Test name
Test status
Simulation time 330609822 ps
CPU time 5.16 seconds
Started May 23 12:41:41 PM PDT 24
Finished May 23 12:41:48 PM PDT 24
Peak memory 197924 kb
Host smart-5b6c6db5-064f-41a5-8ecc-605589aac4f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503641028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.2503641028
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.3514289074
Short name T42
Test name
Test status
Simulation time 64059912 ps
CPU time 0.86 seconds
Started May 23 12:41:39 PM PDT 24
Finished May 23 12:41:42 PM PDT 24
Peak memory 213552 kb
Host smart-be72248d-b710-49f2-bd8e-3c2d63f33a50
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514289074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.3514289074
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.2756875541
Short name T575
Test name
Test status
Simulation time 27769478 ps
CPU time 0.82 seconds
Started May 23 12:41:46 PM PDT 24
Finished May 23 12:41:48 PM PDT 24
Peak memory 195080 kb
Host smart-8bea5bf2-0893-4346-91a4-22ad37f857b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756875541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.2756875541
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.1114316628
Short name T666
Test name
Test status
Simulation time 67030770 ps
CPU time 1.2 seconds
Started May 23 12:41:39 PM PDT 24
Finished May 23 12:41:42 PM PDT 24
Peak memory 195548 kb
Host smart-ab6bf5f9-83b2-4a4d-a8b9-cfa21435a6f2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114316628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.1114316628
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.1976903588
Short name T377
Test name
Test status
Simulation time 54846808656 ps
CPU time 99.14 seconds
Started May 23 12:41:47 PM PDT 24
Finished May 23 12:43:27 PM PDT 24
Peak memory 198132 kb
Host smart-1ec40d42-caf1-4ac9-8aaa-0e28d3291787
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976903588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.1976903588
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.2758370306
Short name T45
Test name
Test status
Simulation time 11109586 ps
CPU time 0.64 seconds
Started May 23 12:41:53 PM PDT 24
Finished May 23 12:41:56 PM PDT 24
Peak memory 194484 kb
Host smart-c32acf7d-4549-4830-8c62-b042842e3577
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758370306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.2758370306
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.1138272000
Short name T251
Test name
Test status
Simulation time 119009283 ps
CPU time 0.86 seconds
Started May 23 12:41:43 PM PDT 24
Finished May 23 12:41:45 PM PDT 24
Peak memory 196596 kb
Host smart-331d434a-1e79-4c24-8e83-0cb467f28d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138272000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.1138272000
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.1939457218
Short name T547
Test name
Test status
Simulation time 3078753169 ps
CPU time 16.4 seconds
Started May 23 12:41:51 PM PDT 24
Finished May 23 12:42:10 PM PDT 24
Peak memory 196852 kb
Host smart-d8e884c7-b926-4afa-8f93-1d9d534d6b1f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939457218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.1939457218
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.2651493188
Short name T234
Test name
Test status
Simulation time 464741931 ps
CPU time 1.02 seconds
Started May 23 12:41:49 PM PDT 24
Finished May 23 12:41:52 PM PDT 24
Peak memory 196236 kb
Host smart-c14bc079-c5e6-48cf-af1a-c483f611b910
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651493188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.2651493188
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.3560882139
Short name T129
Test name
Test status
Simulation time 273594771 ps
CPU time 1.27 seconds
Started May 23 12:41:49 PM PDT 24
Finished May 23 12:41:51 PM PDT 24
Peak memory 196704 kb
Host smart-debc24a7-4573-4ad7-8406-8f93e37dce06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560882139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.3560882139
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.1157501190
Short name T637
Test name
Test status
Simulation time 95478628 ps
CPU time 1.13 seconds
Started May 23 12:41:50 PM PDT 24
Finished May 23 12:41:53 PM PDT 24
Peak memory 197248 kb
Host smart-ba2a5fd5-d08a-4455-a61d-757e845a2353
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157501190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.1157501190
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.785317109
Short name T275
Test name
Test status
Simulation time 129372801 ps
CPU time 2.96 seconds
Started May 23 12:41:50 PM PDT 24
Finished May 23 12:41:55 PM PDT 24
Peak memory 197932 kb
Host smart-3c444bfd-3809-4edc-b1a9-9a2ea6eaf95b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785317109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.785317109
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.2121370507
Short name T518
Test name
Test status
Simulation time 118120537 ps
CPU time 1.31 seconds
Started May 23 12:41:37 PM PDT 24
Finished May 23 12:41:40 PM PDT 24
Peak memory 197900 kb
Host smart-28c968b2-e4b3-43cb-8d4d-0310da6cb2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121370507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.2121370507
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.3267765873
Short name T222
Test name
Test status
Simulation time 236281953 ps
CPU time 0.82 seconds
Started May 23 12:41:38 PM PDT 24
Finished May 23 12:41:40 PM PDT 24
Peak memory 196572 kb
Host smart-86519482-abf3-4e70-931c-7ca7fe8a2474
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267765873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.3267765873
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.4020537999
Short name T542
Test name
Test status
Simulation time 330165244 ps
CPU time 3.89 seconds
Started May 23 12:41:49 PM PDT 24
Finished May 23 12:41:55 PM PDT 24
Peak memory 197432 kb
Host smart-ca1cc4df-2d5f-4fed-a1e1-15aee9c1c917
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020537999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.4020537999
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.3847144587
Short name T43
Test name
Test status
Simulation time 853512306 ps
CPU time 0.76 seconds
Started May 23 12:41:50 PM PDT 24
Finished May 23 12:41:53 PM PDT 24
Peak memory 213548 kb
Host smart-c477faad-323b-4430-a717-93673ecc6589
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847144587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.3847144587
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.703500155
Short name T264
Test name
Test status
Simulation time 89915087 ps
CPU time 0.91 seconds
Started May 23 12:41:45 PM PDT 24
Finished May 23 12:41:47 PM PDT 24
Peak memory 195852 kb
Host smart-02d4956d-bd9e-4b88-9367-164941138238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703500155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.703500155
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.1951689236
Short name T667
Test name
Test status
Simulation time 825742488 ps
CPU time 0.98 seconds
Started May 23 12:41:43 PM PDT 24
Finished May 23 12:41:45 PM PDT 24
Peak memory 196396 kb
Host smart-5262f58b-19cb-48b4-be7a-2aa2298860d4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951689236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.1951689236
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.116479715
Short name T511
Test name
Test status
Simulation time 7005747242 ps
CPU time 87.64 seconds
Started May 23 12:41:49 PM PDT 24
Finished May 23 12:43:17 PM PDT 24
Peak memory 198120 kb
Host smart-bd9917fc-b899-421f-b543-6fdac1529a7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116479715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gp
io_stress_all.116479715
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.3793801859
Short name T79
Test name
Test status
Simulation time 22092236 ps
CPU time 0.54 seconds
Started May 23 12:42:18 PM PDT 24
Finished May 23 12:42:19 PM PDT 24
Peak memory 193792 kb
Host smart-adf6adb2-8ace-401c-9e30-e9d9ee2c4940
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793801859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.3793801859
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.2403595604
Short name T242
Test name
Test status
Simulation time 442619522 ps
CPU time 0.9 seconds
Started May 23 12:42:23 PM PDT 24
Finished May 23 12:42:26 PM PDT 24
Peak memory 196516 kb
Host smart-50f7b6b3-fbfc-41a6-90d8-6f30d09a75af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403595604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.2403595604
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.3725034618
Short name T267
Test name
Test status
Simulation time 2417010650 ps
CPU time 21.45 seconds
Started May 23 12:42:21 PM PDT 24
Finished May 23 12:42:44 PM PDT 24
Peak memory 195524 kb
Host smart-50b66877-f4bd-45a0-af99-d7457659f43a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725034618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.3725034618
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.2754795364
Short name T569
Test name
Test status
Simulation time 67105736 ps
CPU time 1.06 seconds
Started May 23 12:42:23 PM PDT 24
Finished May 23 12:42:26 PM PDT 24
Peak memory 196400 kb
Host smart-2b0025a6-9ab0-4f6f-a922-3e3bdcad896f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754795364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.2754795364
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.627766164
Short name T601
Test name
Test status
Simulation time 82259279 ps
CPU time 0.74 seconds
Started May 23 12:42:22 PM PDT 24
Finished May 23 12:42:25 PM PDT 24
Peak memory 196128 kb
Host smart-3a88a111-cb48-42a9-ab15-3914f751f8fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627766164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.627766164
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.1214773218
Short name T16
Test name
Test status
Simulation time 159818196 ps
CPU time 2.99 seconds
Started May 23 12:42:17 PM PDT 24
Finished May 23 12:42:21 PM PDT 24
Peak memory 197908 kb
Host smart-98060a34-8fcf-4b8c-b32f-4bb47ddc6f51
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214773218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.1214773218
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.1400565425
Short name T494
Test name
Test status
Simulation time 82914605 ps
CPU time 1.69 seconds
Started May 23 12:42:20 PM PDT 24
Finished May 23 12:42:24 PM PDT 24
Peak memory 195856 kb
Host smart-e20e048d-16e6-4fad-9b16-7a6c35dc5411
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400565425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.1400565425
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.733722694
Short name T78
Test name
Test status
Simulation time 46350127 ps
CPU time 1.05 seconds
Started May 23 12:42:17 PM PDT 24
Finished May 23 12:42:19 PM PDT 24
Peak memory 196676 kb
Host smart-d3e58f4a-0d2b-4a98-abbb-bcd18344af95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733722694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.733722694
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.4079905850
Short name T704
Test name
Test status
Simulation time 88720848 ps
CPU time 1 seconds
Started May 23 12:42:23 PM PDT 24
Finished May 23 12:42:26 PM PDT 24
Peak memory 195816 kb
Host smart-930f46b8-ad61-4cf6-9863-235bec972665
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079905850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.4079905850
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.2238264000
Short name T510
Test name
Test status
Simulation time 156427188 ps
CPU time 2.68 seconds
Started May 23 12:42:17 PM PDT 24
Finished May 23 12:42:20 PM PDT 24
Peak memory 197936 kb
Host smart-ae72e54d-d06d-493b-8a0d-e741fe0fc32e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238264000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.2238264000
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.2640316638
Short name T164
Test name
Test status
Simulation time 61000832 ps
CPU time 1.26 seconds
Started May 23 12:42:23 PM PDT 24
Finished May 23 12:42:27 PM PDT 24
Peak memory 195428 kb
Host smart-7cf27784-3ea6-4357-b5bb-7d5cb237bef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640316638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.2640316638
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.4260896673
Short name T679
Test name
Test status
Simulation time 215145293 ps
CPU time 1.02 seconds
Started May 23 12:42:22 PM PDT 24
Finished May 23 12:42:25 PM PDT 24
Peak memory 195584 kb
Host smart-6676a2d7-f65d-44ab-b688-1bc65f562958
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260896673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.4260896673
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.3729627400
Short name T10
Test name
Test status
Simulation time 27100332160 ps
CPU time 76.48 seconds
Started May 23 12:42:18 PM PDT 24
Finished May 23 12:43:36 PM PDT 24
Peak memory 198024 kb
Host smart-78c2a764-024e-4915-baa7-586703002f26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729627400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.3729627400
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.3634285286
Short name T693
Test name
Test status
Simulation time 37839859 ps
CPU time 0.58 seconds
Started May 23 12:42:22 PM PDT 24
Finished May 23 12:42:25 PM PDT 24
Peak memory 193732 kb
Host smart-9f611475-7f18-4144-afc5-f5311c196909
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634285286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.3634285286
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.831079324
Short name T668
Test name
Test status
Simulation time 15203533 ps
CPU time 0.6 seconds
Started May 23 12:42:22 PM PDT 24
Finished May 23 12:42:25 PM PDT 24
Peak memory 193876 kb
Host smart-08fa3aad-8d99-475a-a15f-8206a347d4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831079324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.831079324
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.2535429528
Short name T190
Test name
Test status
Simulation time 1534724525 ps
CPU time 18.41 seconds
Started May 23 12:42:16 PM PDT 24
Finished May 23 12:42:35 PM PDT 24
Peak memory 197860 kb
Host smart-fd2a3ac8-6fe1-428f-b0cc-28df9331fed0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535429528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.2535429528
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.96859101
Short name T641
Test name
Test status
Simulation time 80072963 ps
CPU time 0.71 seconds
Started May 23 12:42:19 PM PDT 24
Finished May 23 12:42:21 PM PDT 24
Peak memory 194384 kb
Host smart-3f5d28c8-acfd-4d9e-bf7e-81667934d1d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96859101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.96859101
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.1756584894
Short name T60
Test name
Test status
Simulation time 41587551 ps
CPU time 1.07 seconds
Started May 23 12:42:22 PM PDT 24
Finished May 23 12:42:25 PM PDT 24
Peak memory 195800 kb
Host smart-f764c8cc-cb9b-4f74-ac48-1a8f4b8c7f85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756584894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.1756584894
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.4285546551
Short name T82
Test name
Test status
Simulation time 77035465 ps
CPU time 3.16 seconds
Started May 23 12:42:22 PM PDT 24
Finished May 23 12:42:27 PM PDT 24
Peak memory 197968 kb
Host smart-40755303-1b45-4fc9-a596-4a41c0f6b37a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285546551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.4285546551
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.569722576
Short name T480
Test name
Test status
Simulation time 586127899 ps
CPU time 3.01 seconds
Started May 23 12:42:24 PM PDT 24
Finished May 23 12:42:30 PM PDT 24
Peak memory 197064 kb
Host smart-e6ecb8f2-22a0-4bb9-a203-2109107b711d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569722576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger.
569722576
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.2515369555
Short name T534
Test name
Test status
Simulation time 82031095 ps
CPU time 0.77 seconds
Started May 23 12:42:23 PM PDT 24
Finished May 23 12:42:27 PM PDT 24
Peak memory 195216 kb
Host smart-f11516e6-256b-4fb5-a295-467fa06907ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515369555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.2515369555
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.2032039935
Short name T359
Test name
Test status
Simulation time 285192415 ps
CPU time 1.34 seconds
Started May 23 12:42:16 PM PDT 24
Finished May 23 12:42:18 PM PDT 24
Peak memory 196856 kb
Host smart-60288aa2-53d5-4d44-9da3-f025204a8e9a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032039935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.2032039935
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.3341151704
Short name T334
Test name
Test status
Simulation time 154832101 ps
CPU time 2.21 seconds
Started May 23 12:42:22 PM PDT 24
Finished May 23 12:42:27 PM PDT 24
Peak memory 197856 kb
Host smart-9cc5bfa9-cab9-4d7c-960c-61542adb75e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341151704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.3341151704
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.989320968
Short name T188
Test name
Test status
Simulation time 174759483 ps
CPU time 1.4 seconds
Started May 23 12:42:21 PM PDT 24
Finished May 23 12:42:25 PM PDT 24
Peak memory 196548 kb
Host smart-f8ff0e81-c3b5-444a-a46c-bc9cd57bd595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989320968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.989320968
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.3114326429
Short name T373
Test name
Test status
Simulation time 164285096 ps
CPU time 1.22 seconds
Started May 23 12:42:22 PM PDT 24
Finished May 23 12:42:25 PM PDT 24
Peak memory 196752 kb
Host smart-941891f0-8d05-4c23-aea6-ad0aa71d3d66
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114326429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.3114326429
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.3410099161
Short name T437
Test name
Test status
Simulation time 10787634870 ps
CPU time 43.17 seconds
Started May 23 12:42:19 PM PDT 24
Finished May 23 12:43:04 PM PDT 24
Peak memory 198144 kb
Host smart-d9b10411-4689-4ac1-baa8-4a0f1d32b2aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410099161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.3410099161
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.4179711233
Short name T84
Test name
Test status
Simulation time 42740116327 ps
CPU time 1257.65 seconds
Started May 23 12:42:17 PM PDT 24
Finished May 23 01:03:16 PM PDT 24
Peak memory 198136 kb
Host smart-8a4f4198-7bfc-4e23-b0d3-0a3482fcbedd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4179711233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.4179711233
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_alert_test.1718822527
Short name T544
Test name
Test status
Simulation time 17792791 ps
CPU time 0.59 seconds
Started May 23 12:42:22 PM PDT 24
Finished May 23 12:42:25 PM PDT 24
Peak memory 193780 kb
Host smart-1f72e3c1-b830-4885-b5e0-24782b6bf427
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718822527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.1718822527
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.850516352
Short name T362
Test name
Test status
Simulation time 25877972 ps
CPU time 0.78 seconds
Started May 23 12:42:17 PM PDT 24
Finished May 23 12:42:19 PM PDT 24
Peak memory 196236 kb
Host smart-dd0b1111-849d-4815-a0fc-5204aa78dd87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850516352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.850516352
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.3235710999
Short name T419
Test name
Test status
Simulation time 1922753530 ps
CPU time 25.86 seconds
Started May 23 12:42:18 PM PDT 24
Finished May 23 12:42:45 PM PDT 24
Peak memory 196816 kb
Host smart-7b61721a-70ef-4108-8bb8-fca96dd75204
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235710999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.3235710999
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.1090220108
Short name T337
Test name
Test status
Simulation time 140847505 ps
CPU time 0.67 seconds
Started May 23 12:42:19 PM PDT 24
Finished May 23 12:42:21 PM PDT 24
Peak memory 195112 kb
Host smart-541942af-54d7-4f91-81eb-f562a71e0976
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090220108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.1090220108
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.3756034563
Short name T529
Test name
Test status
Simulation time 82694901 ps
CPU time 3.03 seconds
Started May 23 12:42:18 PM PDT 24
Finished May 23 12:42:22 PM PDT 24
Peak memory 197816 kb
Host smart-15d3fce9-542d-41cf-bb23-c6d76cad60ca
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756034563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.3756034563
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.2521858139
Short name T312
Test name
Test status
Simulation time 147787516 ps
CPU time 1.17 seconds
Started May 23 12:42:22 PM PDT 24
Finished May 23 12:42:26 PM PDT 24
Peak memory 196112 kb
Host smart-00fc4858-db37-44ad-92df-bc7610aa5cd8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521858139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.2521858139
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.1103388400
Short name T674
Test name
Test status
Simulation time 79584547 ps
CPU time 0.98 seconds
Started May 23 12:42:18 PM PDT 24
Finished May 23 12:42:20 PM PDT 24
Peak memory 196408 kb
Host smart-f5d59b5f-b734-4850-94c8-51d842fd7089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103388400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.1103388400
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.562055163
Short name T375
Test name
Test status
Simulation time 149231072 ps
CPU time 1 seconds
Started May 23 12:42:21 PM PDT 24
Finished May 23 12:42:24 PM PDT 24
Peak memory 196508 kb
Host smart-acc5cff5-e38d-479a-9a7f-9bf4f9f33477
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562055163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullup
_pulldown.562055163
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.1627255323
Short name T366
Test name
Test status
Simulation time 113639997 ps
CPU time 1.45 seconds
Started May 23 12:42:18 PM PDT 24
Finished May 23 12:42:21 PM PDT 24
Peak memory 197824 kb
Host smart-5078a6ea-d792-49e2-b8c1-192a6de09c31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627255323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.1627255323
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.2016471360
Short name T317
Test name
Test status
Simulation time 132360089 ps
CPU time 0.73 seconds
Started May 23 12:42:18 PM PDT 24
Finished May 23 12:42:20 PM PDT 24
Peak memory 194824 kb
Host smart-246f1278-a9fb-41d7-aabf-acc9a197af21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016471360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.2016471360
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.3476602429
Short name T697
Test name
Test status
Simulation time 209241950 ps
CPU time 1.18 seconds
Started May 23 12:42:15 PM PDT 24
Finished May 23 12:42:17 PM PDT 24
Peak memory 195732 kb
Host smart-6680eae7-4c6d-40b2-b492-8c3314116277
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476602429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.3476602429
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.2237144114
Short name T639
Test name
Test status
Simulation time 12011647778 ps
CPU time 178.58 seconds
Started May 23 12:42:22 PM PDT 24
Finished May 23 12:45:22 PM PDT 24
Peak memory 198136 kb
Host smart-96c031ee-bdfd-4012-9486-16d18f0e3f73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237144114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.2237144114
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.1905438114
Short name T67
Test name
Test status
Simulation time 475596484365 ps
CPU time 678.12 seconds
Started May 23 12:42:16 PM PDT 24
Finished May 23 12:53:35 PM PDT 24
Peak memory 198168 kb
Host smart-1a9fae58-855e-4dc4-9ead-6035f23eb7fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1905438114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.1905438114
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.1201746943
Short name T280
Test name
Test status
Simulation time 140990369 ps
CPU time 0.57 seconds
Started May 23 12:42:20 PM PDT 24
Finished May 23 12:42:22 PM PDT 24
Peak memory 194480 kb
Host smart-c8f191a2-c031-4930-aaaf-b2425c9c54e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201746943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.1201746943
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.1375648492
Short name T165
Test name
Test status
Simulation time 34028569 ps
CPU time 0.67 seconds
Started May 23 12:42:24 PM PDT 24
Finished May 23 12:42:28 PM PDT 24
Peak memory 194776 kb
Host smart-e44abd5b-cb69-4ebd-9c37-eacd6199ae38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375648492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.1375648492
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.954507302
Short name T130
Test name
Test status
Simulation time 128677606 ps
CPU time 4.91 seconds
Started May 23 12:42:18 PM PDT 24
Finished May 23 12:42:24 PM PDT 24
Peak memory 195904 kb
Host smart-1f2db875-c7ce-4d85-974d-baaf18183baa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954507302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stres
s.954507302
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.2883013028
Short name T551
Test name
Test status
Simulation time 51863644 ps
CPU time 0.89 seconds
Started May 23 12:42:23 PM PDT 24
Finished May 23 12:42:28 PM PDT 24
Peak memory 195928 kb
Host smart-e51e71db-2241-4b0c-b23a-bd455ea7362c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883013028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.2883013028
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.2803227611
Short name T308
Test name
Test status
Simulation time 93621473 ps
CPU time 1.09 seconds
Started May 23 12:42:23 PM PDT 24
Finished May 23 12:42:28 PM PDT 24
Peak memory 195648 kb
Host smart-2ea569e4-e489-44ca-b433-91f000dcf1ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803227611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.2803227611
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.277150733
Short name T327
Test name
Test status
Simulation time 128793413 ps
CPU time 1.37 seconds
Started May 23 12:42:21 PM PDT 24
Finished May 23 12:42:25 PM PDT 24
Peak memory 196356 kb
Host smart-1ca185bd-c1d1-4ee5-9210-6a2fcf3a0044
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277150733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.gpio_intr_with_filter_rand_intr_event.277150733
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.2754198147
Short name T458
Test name
Test status
Simulation time 255264592 ps
CPU time 1.67 seconds
Started May 23 12:42:22 PM PDT 24
Finished May 23 12:42:26 PM PDT 24
Peak memory 195824 kb
Host smart-2ebccc6f-230a-4b7c-baa5-db1a21bd52e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754198147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.2754198147
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.252278505
Short name T449
Test name
Test status
Simulation time 71363784 ps
CPU time 0.94 seconds
Started May 23 12:42:22 PM PDT 24
Finished May 23 12:42:26 PM PDT 24
Peak memory 195864 kb
Host smart-27ef69ed-2f71-4478-9be5-d0c844ae94d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252278505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.252278505
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.1207350737
Short name T411
Test name
Test status
Simulation time 55998098 ps
CPU time 1.21 seconds
Started May 23 12:42:19 PM PDT 24
Finished May 23 12:42:22 PM PDT 24
Peak memory 198016 kb
Host smart-6aaa3118-977d-4a8f-8d64-4a39ec4ee016
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207350737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.1207350737
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.585938361
Short name T657
Test name
Test status
Simulation time 225248429 ps
CPU time 2.79 seconds
Started May 23 12:42:24 PM PDT 24
Finished May 23 12:42:30 PM PDT 24
Peak memory 197836 kb
Host smart-8bbd8037-c728-46a2-b96b-3df74a5a44d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585938361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ran
dom_long_reg_writes_reg_reads.585938361
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.2493521260
Short name T160
Test name
Test status
Simulation time 49351649 ps
CPU time 1.33 seconds
Started May 23 12:42:25 PM PDT 24
Finished May 23 12:42:29 PM PDT 24
Peak memory 195416 kb
Host smart-fdd1e5ef-f71f-4e8f-b6de-23ab02bf95ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493521260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.2493521260
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.3232479642
Short name T265
Test name
Test status
Simulation time 100818640 ps
CPU time 0.77 seconds
Started May 23 12:42:24 PM PDT 24
Finished May 23 12:42:27 PM PDT 24
Peak memory 195204 kb
Host smart-8e25c459-e6f7-47b4-b92a-16035b705dbd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232479642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.3232479642
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.3255336858
Short name T58
Test name
Test status
Simulation time 15083471219 ps
CPU time 191.68 seconds
Started May 23 12:42:21 PM PDT 24
Finished May 23 12:45:34 PM PDT 24
Peak memory 198132 kb
Host smart-665919b4-422c-4f79-b9c1-1ae6a627d879
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255336858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.3255336858
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.2930272440
Short name T215
Test name
Test status
Simulation time 12947766 ps
CPU time 0.59 seconds
Started May 23 12:42:24 PM PDT 24
Finished May 23 12:42:28 PM PDT 24
Peak memory 194500 kb
Host smart-9eb9e597-3591-4ec1-9934-daed2e797262
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930272440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.2930272440
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.4213221534
Short name T684
Test name
Test status
Simulation time 111236448 ps
CPU time 0.61 seconds
Started May 23 12:42:24 PM PDT 24
Finished May 23 12:42:27 PM PDT 24
Peak memory 194628 kb
Host smart-7f86e2de-e8aa-4ecc-9b02-8ac2386347ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213221534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.4213221534
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.3914234241
Short name T241
Test name
Test status
Simulation time 483343449 ps
CPU time 4.64 seconds
Started May 23 12:42:22 PM PDT 24
Finished May 23 12:42:28 PM PDT 24
Peak memory 196496 kb
Host smart-114bad67-c1ff-474b-9c5e-dee16a140644
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914234241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.3914234241
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.658008398
Short name T652
Test name
Test status
Simulation time 354095593 ps
CPU time 1.07 seconds
Started May 23 12:42:23 PM PDT 24
Finished May 23 12:42:27 PM PDT 24
Peak memory 196272 kb
Host smart-e10046e8-6932-465e-b466-11a9203989d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658008398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.658008398
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.3696122522
Short name T677
Test name
Test status
Simulation time 41357225 ps
CPU time 1.18 seconds
Started May 23 12:42:20 PM PDT 24
Finished May 23 12:42:23 PM PDT 24
Peak memory 195968 kb
Host smart-3db722a9-05ee-4bad-a78e-ec161232357d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696122522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.3696122522
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.2119650073
Short name T694
Test name
Test status
Simulation time 69779015 ps
CPU time 2.56 seconds
Started May 23 12:42:20 PM PDT 24
Finished May 23 12:42:24 PM PDT 24
Peak memory 197728 kb
Host smart-fbe42c21-bd56-427a-a3f3-2611e675dd5e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119650073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.2119650073
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.1092657134
Short name T434
Test name
Test status
Simulation time 252009358 ps
CPU time 2.83 seconds
Started May 23 12:42:22 PM PDT 24
Finished May 23 12:42:27 PM PDT 24
Peak memory 197124 kb
Host smart-fcb52950-c8bd-4b87-89b4-f93a0c38bc70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092657134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.1092657134
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.2148861922
Short name T183
Test name
Test status
Simulation time 116657467 ps
CPU time 1.11 seconds
Started May 23 12:42:20 PM PDT 24
Finished May 23 12:42:23 PM PDT 24
Peak memory 195380 kb
Host smart-6bd437e5-d7b9-4ecd-ba41-e4dd1bc9e89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148861922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.2148861922
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.1033965396
Short name T613
Test name
Test status
Simulation time 56031983 ps
CPU time 1.19 seconds
Started May 23 12:42:25 PM PDT 24
Finished May 23 12:42:29 PM PDT 24
Peak memory 196988 kb
Host smart-c6b278de-66ce-47d1-bbc0-942b18f99d74
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033965396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.1033965396
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.3098867108
Short name T397
Test name
Test status
Simulation time 526364848 ps
CPU time 3.12 seconds
Started May 23 12:42:22 PM PDT 24
Finished May 23 12:42:28 PM PDT 24
Peak memory 197868 kb
Host smart-0bb6b8bb-bf61-47c8-a24b-35cf5c0e6483
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098867108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.3098867108
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.484501943
Short name T481
Test name
Test status
Simulation time 198908398 ps
CPU time 1.05 seconds
Started May 23 12:42:22 PM PDT 24
Finished May 23 12:42:25 PM PDT 24
Peak memory 197208 kb
Host smart-fabbbce7-02a1-4c08-854b-43b67389c297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484501943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.484501943
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.3620835324
Short name T140
Test name
Test status
Simulation time 124914355 ps
CPU time 1.05 seconds
Started May 23 12:42:22 PM PDT 24
Finished May 23 12:42:26 PM PDT 24
Peak memory 195396 kb
Host smart-e589b501-e44e-4804-a65f-78d76018773b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620835324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.3620835324
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.2310573818
Short name T524
Test name
Test status
Simulation time 107090552156 ps
CPU time 181.65 seconds
Started May 23 12:42:23 PM PDT 24
Finished May 23 12:45:28 PM PDT 24
Peak memory 198064 kb
Host smart-cda2bf5d-70f8-4eed-8404-076faea27a5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310573818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.2310573818
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.1280628639
Short name T65
Test name
Test status
Simulation time 89435231844 ps
CPU time 1067.58 seconds
Started May 23 12:42:25 PM PDT 24
Finished May 23 01:00:15 PM PDT 24
Peak memory 198164 kb
Host smart-71116062-f099-4d50-97b7-2059e5be6ea7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1280628639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.1280628639
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.577946046
Short name T531
Test name
Test status
Simulation time 12872939 ps
CPU time 0.57 seconds
Started May 23 12:42:19 PM PDT 24
Finished May 23 12:42:21 PM PDT 24
Peak memory 193864 kb
Host smart-36c470e1-35af-4a31-9c11-e1556bac3ece
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577946046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.577946046
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.3605272773
Short name T348
Test name
Test status
Simulation time 25030068 ps
CPU time 0.72 seconds
Started May 23 12:42:22 PM PDT 24
Finished May 23 12:42:25 PM PDT 24
Peak memory 195216 kb
Host smart-faed607a-fbc8-421d-97ce-f73a3d686ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605272773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.3605272773
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.1359365936
Short name T410
Test name
Test status
Simulation time 895444365 ps
CPU time 11.49 seconds
Started May 23 12:42:22 PM PDT 24
Finished May 23 12:42:36 PM PDT 24
Peak memory 196760 kb
Host smart-4829cbbc-7e08-48d7-b9df-1e918e09d417
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359365936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.1359365936
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.3249715161
Short name T149
Test name
Test status
Simulation time 82815638 ps
CPU time 0.95 seconds
Started May 23 12:42:16 PM PDT 24
Finished May 23 12:42:18 PM PDT 24
Peak memory 196584 kb
Host smart-67674c7d-4ec3-4c01-a318-575641c40410
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249715161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.3249715161
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.14253813
Short name T579
Test name
Test status
Simulation time 34984115 ps
CPU time 1.07 seconds
Started May 23 12:42:22 PM PDT 24
Finished May 23 12:42:26 PM PDT 24
Peak memory 195756 kb
Host smart-1a3cf63f-4045-4d6c-ba76-5d9e24193405
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14253813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.14253813
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.2833199390
Short name T376
Test name
Test status
Simulation time 234341003 ps
CPU time 2.49 seconds
Started May 23 12:42:22 PM PDT 24
Finished May 23 12:42:27 PM PDT 24
Peak memory 198040 kb
Host smart-1ba9a0f3-4cb6-4914-be39-2f581eed3734
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833199390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.2833199390
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.2499250835
Short name T656
Test name
Test status
Simulation time 449809314 ps
CPU time 2.56 seconds
Started May 23 12:42:25 PM PDT 24
Finished May 23 12:42:31 PM PDT 24
Peak memory 197184 kb
Host smart-f3f1b460-e10d-42e9-9fcb-cbc45f773848
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499250835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.2499250835
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.3707322484
Short name T132
Test name
Test status
Simulation time 24167080 ps
CPU time 0.99 seconds
Started May 23 12:42:24 PM PDT 24
Finished May 23 12:42:28 PM PDT 24
Peak memory 195724 kb
Host smart-417c905f-c730-426d-9d11-6f4e8a864dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707322484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.3707322484
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.4002651300
Short name T669
Test name
Test status
Simulation time 77840546 ps
CPU time 0.88 seconds
Started May 23 12:42:25 PM PDT 24
Finished May 23 12:42:29 PM PDT 24
Peak memory 196660 kb
Host smart-0cf42cea-b63f-4a71-824b-680a72444019
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002651300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.4002651300
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.1215181755
Short name T710
Test name
Test status
Simulation time 182739335 ps
CPU time 3.08 seconds
Started May 23 12:42:25 PM PDT 24
Finished May 23 12:42:31 PM PDT 24
Peak memory 197912 kb
Host smart-bc785b96-3674-404c-b06d-949cac23e360
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215181755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.1215181755
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.2692747440
Short name T356
Test name
Test status
Simulation time 661125884 ps
CPU time 1.16 seconds
Started May 23 12:42:27 PM PDT 24
Finished May 23 12:42:30 PM PDT 24
Peak memory 195752 kb
Host smart-b0c49172-0d2c-44b4-905c-571a94f3f8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692747440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.2692747440
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.3420678381
Short name T238
Test name
Test status
Simulation time 105590755 ps
CPU time 0.7 seconds
Started May 23 12:42:23 PM PDT 24
Finished May 23 12:42:27 PM PDT 24
Peak memory 194100 kb
Host smart-1eec2ec4-364d-4109-9174-08f5cf97e33f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420678381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.3420678381
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.1673557640
Short name T403
Test name
Test status
Simulation time 31007229621 ps
CPU time 67.27 seconds
Started May 23 12:42:22 PM PDT 24
Finished May 23 12:43:32 PM PDT 24
Peak memory 198136 kb
Host smart-48685c61-7a1d-470e-9ddc-debab7ff95d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673557640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.1673557640
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.2431423851
Short name T521
Test name
Test status
Simulation time 42365679 ps
CPU time 0.59 seconds
Started May 23 12:42:29 PM PDT 24
Finished May 23 12:42:30 PM PDT 24
Peak memory 194680 kb
Host smart-c0d628fa-beec-40b4-8da8-fce0b5bbca77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431423851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.2431423851
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.445303615
Short name T284
Test name
Test status
Simulation time 76472869 ps
CPU time 0.86 seconds
Started May 23 12:42:18 PM PDT 24
Finished May 23 12:42:21 PM PDT 24
Peak memory 195272 kb
Host smart-cad0e52b-aed2-4605-bcb9-de0fa636ed3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445303615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.445303615
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.2976526748
Short name T442
Test name
Test status
Simulation time 324040526 ps
CPU time 16.89 seconds
Started May 23 12:42:23 PM PDT 24
Finished May 23 12:42:43 PM PDT 24
Peak memory 195392 kb
Host smart-a75cf1f2-6a98-471b-8d4a-46e6a1b0253f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976526748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.2976526748
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.3485911965
Short name T133
Test name
Test status
Simulation time 53638901 ps
CPU time 0.61 seconds
Started May 23 12:42:24 PM PDT 24
Finished May 23 12:42:28 PM PDT 24
Peak memory 194352 kb
Host smart-760adc97-1e58-473e-8f7c-905b3f238838
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485911965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.3485911965
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.3855405579
Short name T246
Test name
Test status
Simulation time 391949806 ps
CPU time 1.22 seconds
Started May 23 12:42:19 PM PDT 24
Finished May 23 12:42:22 PM PDT 24
Peak memory 196456 kb
Host smart-02a6f26a-2680-4ad9-971d-e02ef4c917b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855405579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.3855405579
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.1938163162
Short name T110
Test name
Test status
Simulation time 29425430 ps
CPU time 1.26 seconds
Started May 23 12:42:22 PM PDT 24
Finished May 23 12:42:26 PM PDT 24
Peak memory 196572 kb
Host smart-e4b8e0a0-d557-4519-beee-f933573b1ff8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938163162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.1938163162
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.1983722896
Short name T371
Test name
Test status
Simulation time 497212265 ps
CPU time 2.01 seconds
Started May 23 12:42:22 PM PDT 24
Finished May 23 12:42:26 PM PDT 24
Peak memory 195692 kb
Host smart-a284687a-7ed5-4d1a-bf77-538b77392c84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983722896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.1983722896
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.1989828866
Short name T552
Test name
Test status
Simulation time 150180206 ps
CPU time 1.1 seconds
Started May 23 12:42:18 PM PDT 24
Finished May 23 12:42:20 PM PDT 24
Peak memory 196860 kb
Host smart-4f6f5b43-3b3b-4e3a-a656-aaf1e04c9525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989828866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.1989828866
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.3596348318
Short name T340
Test name
Test status
Simulation time 31206143 ps
CPU time 0.79 seconds
Started May 23 12:42:22 PM PDT 24
Finished May 23 12:42:25 PM PDT 24
Peak memory 195492 kb
Host smart-1276c575-ce90-452c-970f-2b57bb44a821
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596348318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.3596348318
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.1618382716
Short name T252
Test name
Test status
Simulation time 360945153 ps
CPU time 5.71 seconds
Started May 23 12:42:22 PM PDT 24
Finished May 23 12:42:30 PM PDT 24
Peak memory 197796 kb
Host smart-d728ee09-496a-441c-812a-74feeedac1ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618382716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.1618382716
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.3535015744
Short name T63
Test name
Test status
Simulation time 163784761 ps
CPU time 1.13 seconds
Started May 23 12:42:22 PM PDT 24
Finished May 23 12:42:25 PM PDT 24
Peak memory 196364 kb
Host smart-464ac171-f3d5-464b-a504-95c24289f041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535015744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.3535015744
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.985272210
Short name T367
Test name
Test status
Simulation time 48283350 ps
CPU time 0.82 seconds
Started May 23 12:42:23 PM PDT 24
Finished May 23 12:42:26 PM PDT 24
Peak memory 195068 kb
Host smart-dbb960d2-ba10-479a-a33a-a709872dbfdc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985272210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.985272210
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.4265752025
Short name T589
Test name
Test status
Simulation time 16120598576 ps
CPU time 100.52 seconds
Started May 23 12:42:35 PM PDT 24
Finished May 23 12:44:17 PM PDT 24
Peak memory 198148 kb
Host smart-7aca0ff6-7470-4340-96b9-16ba61a3f962
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265752025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.4265752025
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.239271937
Short name T627
Test name
Test status
Simulation time 32458143 ps
CPU time 0.57 seconds
Started May 23 12:42:32 PM PDT 24
Finished May 23 12:42:33 PM PDT 24
Peak memory 193988 kb
Host smart-89ba78b5-634b-4a81-a7df-e5d254d6c88a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239271937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.239271937
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.1122644502
Short name T240
Test name
Test status
Simulation time 54478771 ps
CPU time 0.79 seconds
Started May 23 12:42:31 PM PDT 24
Finished May 23 12:42:33 PM PDT 24
Peak memory 195284 kb
Host smart-ab07ac15-d69a-49d0-aa1d-7547c8b1960a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122644502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.1122644502
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.3422969521
Short name T186
Test name
Test status
Simulation time 755716994 ps
CPU time 20.37 seconds
Started May 23 12:42:31 PM PDT 24
Finished May 23 12:42:52 PM PDT 24
Peak memory 195364 kb
Host smart-8441a727-aa59-4d87-afec-fd2fece0960f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422969521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.3422969521
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.4140287204
Short name T533
Test name
Test status
Simulation time 88117487 ps
CPU time 1.01 seconds
Started May 23 12:42:28 PM PDT 24
Finished May 23 12:42:30 PM PDT 24
Peak memory 196420 kb
Host smart-31a41023-0cb4-46b4-8381-03bcb203d347
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140287204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.4140287204
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.1829374150
Short name T288
Test name
Test status
Simulation time 64282726 ps
CPU time 1 seconds
Started May 23 12:42:29 PM PDT 24
Finished May 23 12:42:30 PM PDT 24
Peak memory 196152 kb
Host smart-287d69fd-a4b7-464c-9471-772ff0886548
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829374150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.1829374150
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.671645287
Short name T233
Test name
Test status
Simulation time 33755277 ps
CPU time 1.32 seconds
Started May 23 12:42:29 PM PDT 24
Finished May 23 12:42:31 PM PDT 24
Peak memory 197848 kb
Host smart-56a9d02b-35f7-4c09-868f-c6a544aa840b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671645287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.gpio_intr_with_filter_rand_intr_event.671645287
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.2872654814
Short name T399
Test name
Test status
Simulation time 525891758 ps
CPU time 2.37 seconds
Started May 23 12:42:35 PM PDT 24
Finished May 23 12:42:39 PM PDT 24
Peak memory 195560 kb
Host smart-1ec4f63f-100d-4bd4-a116-b77f2d0434ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872654814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.2872654814
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.4258392405
Short name T484
Test name
Test status
Simulation time 233853135 ps
CPU time 0.96 seconds
Started May 23 12:42:37 PM PDT 24
Finished May 23 12:42:39 PM PDT 24
Peak memory 196480 kb
Host smart-b778fc95-7ba2-46a5-b631-f389a56c0dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258392405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.4258392405
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.869995842
Short name T549
Test name
Test status
Simulation time 56284935 ps
CPU time 1.14 seconds
Started May 23 12:42:36 PM PDT 24
Finished May 23 12:42:39 PM PDT 24
Peak memory 196000 kb
Host smart-9b631fd9-447b-486e-bc40-73f6f91dd943
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869995842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullup
_pulldown.869995842
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.3336327674
Short name T495
Test name
Test status
Simulation time 863346600 ps
CPU time 3.1 seconds
Started May 23 12:42:29 PM PDT 24
Finished May 23 12:42:33 PM PDT 24
Peak memory 197928 kb
Host smart-0ef6d677-ad4a-4404-a81d-3c098ba8e6d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336327674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.3336327674
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.2370574096
Short name T158
Test name
Test status
Simulation time 138447843 ps
CPU time 1.11 seconds
Started May 23 12:42:34 PM PDT 24
Finished May 23 12:42:37 PM PDT 24
Peak memory 195648 kb
Host smart-eaa837f8-55c1-42b5-8458-f4ecb857abdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370574096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.2370574096
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.4060073783
Short name T121
Test name
Test status
Simulation time 229211724 ps
CPU time 1.2 seconds
Started May 23 12:42:36 PM PDT 24
Finished May 23 12:42:39 PM PDT 24
Peak memory 196280 kb
Host smart-3ea3697f-5901-4a1e-b16c-8a850afd68e2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060073783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.4060073783
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.4220417506
Short name T453
Test name
Test status
Simulation time 13103794147 ps
CPU time 87.03 seconds
Started May 23 12:42:33 PM PDT 24
Finished May 23 12:44:01 PM PDT 24
Peak memory 198136 kb
Host smart-62e5c5a4-6ab1-4afd-b195-ec7fe4d2ffb0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220417506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.4220417506
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.1010411644
Short name T468
Test name
Test status
Simulation time 43371737 ps
CPU time 0.57 seconds
Started May 23 12:42:36 PM PDT 24
Finished May 23 12:42:38 PM PDT 24
Peak memory 193860 kb
Host smart-fe1e2e1b-e4dc-44c1-b1b2-f3b014b73cc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010411644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.1010411644
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.651463447
Short name T299
Test name
Test status
Simulation time 56360324 ps
CPU time 0.91 seconds
Started May 23 12:42:39 PM PDT 24
Finished May 23 12:42:42 PM PDT 24
Peak memory 196292 kb
Host smart-8c8fd708-3640-4a77-adb1-7414b5247356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651463447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.651463447
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.595640710
Short name T490
Test name
Test status
Simulation time 344317836 ps
CPU time 9.22 seconds
Started May 23 12:42:32 PM PDT 24
Finished May 23 12:42:42 PM PDT 24
Peak memory 197944 kb
Host smart-dbd45739-8eb9-4dfb-9b14-514773e55d9d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595640710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stres
s.595640710
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.3190488425
Short name T653
Test name
Test status
Simulation time 45606582 ps
CPU time 0.81 seconds
Started May 23 12:42:36 PM PDT 24
Finished May 23 12:42:39 PM PDT 24
Peak memory 195824 kb
Host smart-1cad472f-fa57-4322-8c6a-36e0cad978e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190488425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.3190488425
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.1503549955
Short name T570
Test name
Test status
Simulation time 134592052 ps
CPU time 1.11 seconds
Started May 23 12:42:38 PM PDT 24
Finished May 23 12:42:41 PM PDT 24
Peak memory 195712 kb
Host smart-572e62b9-1aa2-45cf-a14e-bd4060e1c9d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503549955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.1503549955
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.3373334515
Short name T255
Test name
Test status
Simulation time 83107285 ps
CPU time 1.02 seconds
Started May 23 12:42:31 PM PDT 24
Finished May 23 12:42:33 PM PDT 24
Peak memory 197048 kb
Host smart-d546e588-9e7b-414a-85c6-006fd3875b77
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373334515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.3373334515
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.422026855
Short name T514
Test name
Test status
Simulation time 52024342 ps
CPU time 1.67 seconds
Started May 23 12:42:39 PM PDT 24
Finished May 23 12:42:42 PM PDT 24
Peak memory 195988 kb
Host smart-dbb334cd-dcab-41ab-947f-f36836a02309
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422026855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger.
422026855
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.1734988878
Short name T147
Test name
Test status
Simulation time 110836436 ps
CPU time 0.87 seconds
Started May 23 12:42:33 PM PDT 24
Finished May 23 12:42:35 PM PDT 24
Peak memory 196564 kb
Host smart-292c937b-ee54-405d-9864-32e2c9630d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734988878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.1734988878
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.3941171347
Short name T386
Test name
Test status
Simulation time 27224690 ps
CPU time 0.64 seconds
Started May 23 12:42:33 PM PDT 24
Finished May 23 12:42:35 PM PDT 24
Peak memory 194320 kb
Host smart-fe6533b9-df25-4e30-a9bd-3481d2e5fe46
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941171347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.3941171347
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.2169975197
Short name T61
Test name
Test status
Simulation time 218207862 ps
CPU time 2.65 seconds
Started May 23 12:42:31 PM PDT 24
Finished May 23 12:42:35 PM PDT 24
Peak memory 197920 kb
Host smart-af39814b-4bee-4617-98b1-766e4c7f72ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169975197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.2169975197
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.2853572211
Short name T329
Test name
Test status
Simulation time 140770766 ps
CPU time 1.02 seconds
Started May 23 12:42:32 PM PDT 24
Finished May 23 12:42:34 PM PDT 24
Peak memory 195652 kb
Host smart-27197bac-da45-431b-9d6a-dcfdd6718714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853572211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.2853572211
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.851780092
Short name T698
Test name
Test status
Simulation time 117498715 ps
CPU time 1.03 seconds
Started May 23 12:42:36 PM PDT 24
Finished May 23 12:42:38 PM PDT 24
Peak memory 195420 kb
Host smart-31756974-ba05-4254-bfcd-d2135ca61411
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851780092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.851780092
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.1073584148
Short name T606
Test name
Test status
Simulation time 1792353299 ps
CPU time 43.44 seconds
Started May 23 12:42:31 PM PDT 24
Finished May 23 12:43:15 PM PDT 24
Peak memory 197840 kb
Host smart-e3b5561c-643f-4962-aaa7-af471987edde
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073584148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.1073584148
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.3857797200
Short name T463
Test name
Test status
Simulation time 14716602 ps
CPU time 0.57 seconds
Started May 23 12:42:34 PM PDT 24
Finished May 23 12:42:36 PM PDT 24
Peak memory 194772 kb
Host smart-f63cdfc8-6ac7-4e9d-9fb1-da9d68c9885e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857797200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.3857797200
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.2434799962
Short name T422
Test name
Test status
Simulation time 207987267 ps
CPU time 0.91 seconds
Started May 23 12:42:33 PM PDT 24
Finished May 23 12:42:35 PM PDT 24
Peak memory 197208 kb
Host smart-e17a6f6a-5ae7-40dd-9c90-e0ba5cd51dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434799962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.2434799962
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.357342990
Short name T76
Test name
Test status
Simulation time 5948763078 ps
CPU time 15.62 seconds
Started May 23 12:42:36 PM PDT 24
Finished May 23 12:42:53 PM PDT 24
Peak memory 197392 kb
Host smart-fdfffa5a-6f54-44b1-aa2d-b6653eb9956a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357342990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stres
s.357342990
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.4213894949
Short name T648
Test name
Test status
Simulation time 337039294 ps
CPU time 1.09 seconds
Started May 23 12:42:38 PM PDT 24
Finished May 23 12:42:41 PM PDT 24
Peak memory 197736 kb
Host smart-24f2405c-df5b-478d-b44f-170a89550124
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213894949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.4213894949
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.258469331
Short name T571
Test name
Test status
Simulation time 31701499 ps
CPU time 0.74 seconds
Started May 23 12:42:36 PM PDT 24
Finished May 23 12:42:38 PM PDT 24
Peak memory 195408 kb
Host smart-29ee4f9f-2756-4a56-9c5a-2872c1802350
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258469331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.258469331
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.3662510345
Short name T249
Test name
Test status
Simulation time 134018391 ps
CPU time 2.84 seconds
Started May 23 12:42:35 PM PDT 24
Finished May 23 12:42:39 PM PDT 24
Peak memory 197724 kb
Host smart-99e8db31-f047-4b27-ad7a-1bf6732dbd21
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662510345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.3662510345
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.3815818675
Short name T301
Test name
Test status
Simulation time 562584469 ps
CPU time 3.18 seconds
Started May 23 12:42:35 PM PDT 24
Finished May 23 12:42:40 PM PDT 24
Peak memory 197936 kb
Host smart-399b3462-b454-4a5e-b777-d6eb0aac4508
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815818675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.3815818675
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.3460329955
Short name T602
Test name
Test status
Simulation time 103466615 ps
CPU time 0.78 seconds
Started May 23 12:42:31 PM PDT 24
Finished May 23 12:42:33 PM PDT 24
Peak memory 195288 kb
Host smart-b71fc9d9-f4ae-4359-a292-d09528618dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460329955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.3460329955
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.1775975627
Short name T156
Test name
Test status
Simulation time 69592897 ps
CPU time 1.19 seconds
Started May 23 12:42:33 PM PDT 24
Finished May 23 12:42:36 PM PDT 24
Peak memory 195880 kb
Host smart-f538d546-8fd5-43c7-808d-aa5fcf9da25b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775975627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.1775975627
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.3780782752
Short name T325
Test name
Test status
Simulation time 108691224 ps
CPU time 1.7 seconds
Started May 23 12:42:39 PM PDT 24
Finished May 23 12:42:42 PM PDT 24
Peak memory 197916 kb
Host smart-4e1d1067-6ea9-4aef-95c3-295bc7229a7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780782752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.3780782752
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.252284920
Short name T232
Test name
Test status
Simulation time 270212019 ps
CPU time 1.18 seconds
Started May 23 12:42:38 PM PDT 24
Finished May 23 12:42:41 PM PDT 24
Peak memory 196304 kb
Host smart-ebaff896-7962-49a8-8dfc-a5c580821ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252284920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.252284920
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.149997696
Short name T332
Test name
Test status
Simulation time 130619474 ps
CPU time 0.91 seconds
Started May 23 12:42:35 PM PDT 24
Finished May 23 12:42:37 PM PDT 24
Peak memory 196364 kb
Host smart-84797b43-a372-45e7-8b07-fbc2aff6c681
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149997696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.149997696
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.2162847987
Short name T646
Test name
Test status
Simulation time 5751695514 ps
CPU time 37.66 seconds
Started May 23 12:42:33 PM PDT 24
Finished May 23 12:43:12 PM PDT 24
Peak memory 197968 kb
Host smart-26f785e4-52fc-4626-8514-a507916a45a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162847987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.2162847987
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.4054428258
Short name T540
Test name
Test status
Simulation time 258578968609 ps
CPU time 2576.44 seconds
Started May 23 12:42:36 PM PDT 24
Finished May 23 01:25:34 PM PDT 24
Peak memory 198096 kb
Host smart-88b61fc5-90ab-4fb7-8b20-77153507e402
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4054428258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.4054428258
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.1484289829
Short name T428
Test name
Test status
Simulation time 26813167 ps
CPU time 0.53 seconds
Started May 23 12:41:51 PM PDT 24
Finished May 23 12:41:54 PM PDT 24
Peak memory 193812 kb
Host smart-785e82fd-c067-4da5-ad1b-9a9417dd5816
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484289829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.1484289829
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.2616984387
Short name T179
Test name
Test status
Simulation time 131191101 ps
CPU time 0.79 seconds
Started May 23 12:41:50 PM PDT 24
Finished May 23 12:41:53 PM PDT 24
Peak memory 195968 kb
Host smart-2442f992-162c-4a25-8fb7-abd746362274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616984387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.2616984387
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.3918121017
Short name T378
Test name
Test status
Simulation time 698197765 ps
CPU time 24.02 seconds
Started May 23 12:41:52 PM PDT 24
Finished May 23 12:42:19 PM PDT 24
Peak memory 196568 kb
Host smart-b45424b8-0138-4c8f-98d3-b4b9ae0e7f4a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918121017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.3918121017
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.2059461648
Short name T426
Test name
Test status
Simulation time 79898047 ps
CPU time 0.68 seconds
Started May 23 12:41:49 PM PDT 24
Finished May 23 12:41:51 PM PDT 24
Peak memory 194696 kb
Host smart-c6675345-7b79-41ce-a6f4-983fec55d9a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059461648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.2059461648
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.1421273975
Short name T572
Test name
Test status
Simulation time 110705075 ps
CPU time 1.22 seconds
Started May 23 12:41:51 PM PDT 24
Finished May 23 12:41:55 PM PDT 24
Peak memory 197088 kb
Host smart-95ffe4cd-98a4-432a-b975-effd4f53c5fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421273975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.1421273975
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.2285772221
Short name T640
Test name
Test status
Simulation time 297594047 ps
CPU time 3.08 seconds
Started May 23 12:41:49 PM PDT 24
Finished May 23 12:41:53 PM PDT 24
Peak memory 197940 kb
Host smart-b77fa311-a457-4a84-b7e0-aab2ef196702
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285772221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.2285772221
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.3973074249
Short name T635
Test name
Test status
Simulation time 663785211 ps
CPU time 3.14 seconds
Started May 23 12:41:49 PM PDT 24
Finished May 23 12:41:53 PM PDT 24
Peak memory 196456 kb
Host smart-ea4b99fa-1e3a-4987-be7f-2e80302e3e75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973074249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
3973074249
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.331475398
Short name T632
Test name
Test status
Simulation time 175291488 ps
CPU time 0.99 seconds
Started May 23 12:41:49 PM PDT 24
Finished May 23 12:41:52 PM PDT 24
Peak memory 196436 kb
Host smart-3bbc1729-fe33-45b5-a32e-dadaf17573cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331475398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.331475398
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.344537369
Short name T587
Test name
Test status
Simulation time 54286663 ps
CPU time 1.15 seconds
Started May 23 12:41:50 PM PDT 24
Finished May 23 12:41:54 PM PDT 24
Peak memory 195820 kb
Host smart-79a136fb-4a9f-45f4-abec-61000d615eb2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344537369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup_
pulldown.344537369
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.3656738118
Short name T300
Test name
Test status
Simulation time 154577644 ps
CPU time 2.04 seconds
Started May 23 12:41:50 PM PDT 24
Finished May 23 12:41:55 PM PDT 24
Peak memory 197856 kb
Host smart-0ccc192f-a13f-4504-9a8d-16671f069e7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656738118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.3656738118
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.2637010369
Short name T56
Test name
Test status
Simulation time 177516650 ps
CPU time 0.92 seconds
Started May 23 12:41:51 PM PDT 24
Finished May 23 12:41:55 PM PDT 24
Peak memory 214728 kb
Host smart-5fead341-6153-4e50-8a23-ac730e501b21
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637010369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.2637010369
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.3621890592
Short name T269
Test name
Test status
Simulation time 38253500 ps
CPU time 1.08 seconds
Started May 23 12:41:49 PM PDT 24
Finished May 23 12:41:51 PM PDT 24
Peak memory 195676 kb
Host smart-78ffc426-cc64-4cb4-9b63-fd01818a264b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621890592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.3621890592
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.540903549
Short name T291
Test name
Test status
Simulation time 83036630 ps
CPU time 1.44 seconds
Started May 23 12:41:51 PM PDT 24
Finished May 23 12:41:55 PM PDT 24
Peak memory 197940 kb
Host smart-c98588c8-3ef7-4231-9cb4-cccef120de6c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540903549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.540903549
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.467072782
Short name T21
Test name
Test status
Simulation time 47751037159 ps
CPU time 141.25 seconds
Started May 23 12:41:50 PM PDT 24
Finished May 23 12:44:14 PM PDT 24
Peak memory 198092 kb
Host smart-06eff6f4-8333-433d-8c3a-778f4a45e3ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467072782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gp
io_stress_all.467072782
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.2700987338
Short name T436
Test name
Test status
Simulation time 50035918 ps
CPU time 0.56 seconds
Started May 23 12:42:37 PM PDT 24
Finished May 23 12:42:40 PM PDT 24
Peak memory 193840 kb
Host smart-67591176-f23b-4568-8780-94be4697ae26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700987338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.2700987338
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.444081610
Short name T660
Test name
Test status
Simulation time 66348949 ps
CPU time 0.8 seconds
Started May 23 12:42:37 PM PDT 24
Finished May 23 12:42:40 PM PDT 24
Peak memory 195156 kb
Host smart-4104ffa3-c59d-4251-a09a-12ec0c3371b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444081610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.444081610
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.1369088989
Short name T592
Test name
Test status
Simulation time 130328952 ps
CPU time 7.14 seconds
Started May 23 12:42:35 PM PDT 24
Finished May 23 12:42:44 PM PDT 24
Peak memory 196712 kb
Host smart-6fa3d6ea-273d-4ebc-855e-a68a1f713f6c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369088989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.1369088989
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.51142530
Short name T345
Test name
Test status
Simulation time 205336962 ps
CPU time 0.63 seconds
Started May 23 12:42:37 PM PDT 24
Finished May 23 12:42:40 PM PDT 24
Peak memory 195116 kb
Host smart-3142d94d-1f3e-4bc4-b7cf-41370ff25bf4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51142530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.51142530
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.3025968908
Short name T322
Test name
Test status
Simulation time 85352294 ps
CPU time 1.31 seconds
Started May 23 12:42:35 PM PDT 24
Finished May 23 12:42:38 PM PDT 24
Peak memory 195912 kb
Host smart-f0644daa-bee1-4094-aa72-e17c4f84ff62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025968908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.3025968908
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.2410619798
Short name T111
Test name
Test status
Simulation time 339368322 ps
CPU time 3.24 seconds
Started May 23 12:42:33 PM PDT 24
Finished May 23 12:42:37 PM PDT 24
Peak memory 197972 kb
Host smart-f7602164-7d47-493c-adf2-6a7691fbf8e1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410619798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.2410619798
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.4186736152
Short name T270
Test name
Test status
Simulation time 377279824 ps
CPU time 2.68 seconds
Started May 23 12:42:35 PM PDT 24
Finished May 23 12:42:39 PM PDT 24
Peak memory 196960 kb
Host smart-37c0e4f0-74f9-4c8b-8455-724a106c4de1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186736152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.4186736152
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.546676127
Short name T245
Test name
Test status
Simulation time 76681524 ps
CPU time 1.27 seconds
Started May 23 12:42:38 PM PDT 24
Finished May 23 12:42:41 PM PDT 24
Peak memory 196856 kb
Host smart-601c2a58-afc4-4fad-9c67-1fc0119b897c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546676127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.546676127
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.3828975020
Short name T272
Test name
Test status
Simulation time 114150981 ps
CPU time 1.1 seconds
Started May 23 12:42:39 PM PDT 24
Finished May 23 12:42:42 PM PDT 24
Peak memory 195932 kb
Host smart-3963df74-25f9-464d-839d-ad7c38532438
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828975020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.3828975020
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.3090570350
Short name T658
Test name
Test status
Simulation time 122626699 ps
CPU time 2.32 seconds
Started May 23 12:42:38 PM PDT 24
Finished May 23 12:42:42 PM PDT 24
Peak memory 197904 kb
Host smart-a751ec0e-dd65-4f78-8377-0e39a4239e34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090570350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.3090570350
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.1352464895
Short name T708
Test name
Test status
Simulation time 76840999 ps
CPU time 1.38 seconds
Started May 23 12:42:37 PM PDT 24
Finished May 23 12:42:41 PM PDT 24
Peak memory 196704 kb
Host smart-197daa04-77d5-4d43-a958-d567d247c27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352464895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.1352464895
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.1121849938
Short name T615
Test name
Test status
Simulation time 72925787 ps
CPU time 1.03 seconds
Started May 23 12:42:34 PM PDT 24
Finished May 23 12:42:37 PM PDT 24
Peak memory 195596 kb
Host smart-7edeeeb1-db51-4157-8570-684a92823e61
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121849938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.1121849938
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.1715432980
Short name T1
Test name
Test status
Simulation time 48332406940 ps
CPU time 131.18 seconds
Started May 23 12:42:37 PM PDT 24
Finished May 23 12:44:50 PM PDT 24
Peak memory 198076 kb
Host smart-f04ab469-bf11-46ba-950d-1bf74926f595
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715432980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.1715432980
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.3683146965
Short name T389
Test name
Test status
Simulation time 43680250 ps
CPU time 0.6 seconds
Started May 23 12:42:33 PM PDT 24
Finished May 23 12:42:35 PM PDT 24
Peak memory 194028 kb
Host smart-52e790c6-6fcd-498a-8846-ada6775f2a18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683146965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.3683146965
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.3674978055
Short name T151
Test name
Test status
Simulation time 138153915 ps
CPU time 0.76 seconds
Started May 23 12:42:38 PM PDT 24
Finished May 23 12:42:41 PM PDT 24
Peak memory 196000 kb
Host smart-b6c3e386-b87f-48f4-9b0d-dd5821021424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674978055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.3674978055
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.3184348076
Short name T662
Test name
Test status
Simulation time 1988603658 ps
CPU time 21.89 seconds
Started May 23 12:42:34 PM PDT 24
Finished May 23 12:42:58 PM PDT 24
Peak memory 195380 kb
Host smart-c0c3f1ee-526d-4436-ab7d-3fb96a4627ea
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184348076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.3184348076
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.739836836
Short name T563
Test name
Test status
Simulation time 44371170 ps
CPU time 0.81 seconds
Started May 23 12:42:39 PM PDT 24
Finished May 23 12:42:41 PM PDT 24
Peak memory 195828 kb
Host smart-2ca273a4-30e0-4ecf-a0ab-d830d678caa6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739836836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.739836836
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.148662314
Short name T465
Test name
Test status
Simulation time 285634839 ps
CPU time 1.33 seconds
Started May 23 12:42:36 PM PDT 24
Finished May 23 12:42:39 PM PDT 24
Peak memory 196584 kb
Host smart-170a9f42-7c75-4fd0-a47a-1201c3cbc3c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148662314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.148662314
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.2668884641
Short name T483
Test name
Test status
Simulation time 63186549 ps
CPU time 2.55 seconds
Started May 23 12:42:38 PM PDT 24
Finished May 23 12:42:42 PM PDT 24
Peak memory 197968 kb
Host smart-c4c71374-3d7c-4bb9-82c2-599f57ce30ca
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668884641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.2668884641
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.3502923393
Short name T307
Test name
Test status
Simulation time 144607287 ps
CPU time 1.62 seconds
Started May 23 12:42:38 PM PDT 24
Finished May 23 12:42:42 PM PDT 24
Peak memory 196596 kb
Host smart-08a35059-1113-4c10-8573-d88ae98dd40a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502923393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.3502923393
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.1555742575
Short name T391
Test name
Test status
Simulation time 39734173 ps
CPU time 0.65 seconds
Started May 23 12:42:40 PM PDT 24
Finished May 23 12:42:42 PM PDT 24
Peak memory 194168 kb
Host smart-a73ee953-3560-4155-8673-ff90d0bb73ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555742575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.1555742575
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.523580209
Short name T15
Test name
Test status
Simulation time 140010387 ps
CPU time 0.94 seconds
Started May 23 12:42:40 PM PDT 24
Finished May 23 12:42:42 PM PDT 24
Peak memory 196528 kb
Host smart-f2eb1b31-8c63-4ee7-87dd-b23ec668b422
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523580209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullup
_pulldown.523580209
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.2715071071
Short name T506
Test name
Test status
Simulation time 1409096114 ps
CPU time 4.85 seconds
Started May 23 12:42:37 PM PDT 24
Finished May 23 12:42:44 PM PDT 24
Peak memory 197916 kb
Host smart-b346f29c-0f83-43cf-957b-96534b73714e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715071071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.2715071071
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.2217662505
Short name T319
Test name
Test status
Simulation time 110344284 ps
CPU time 1.08 seconds
Started May 23 12:42:35 PM PDT 24
Finished May 23 12:42:38 PM PDT 24
Peak memory 195832 kb
Host smart-8a4dc4df-ad94-4aa6-928c-3cce042ceb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217662505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.2217662505
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.3305302429
Short name T64
Test name
Test status
Simulation time 129798887 ps
CPU time 0.95 seconds
Started May 23 12:42:40 PM PDT 24
Finished May 23 12:42:42 PM PDT 24
Peak memory 195364 kb
Host smart-aea697ae-491f-4261-83a0-a9d193c505cd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305302429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.3305302429
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.2595094881
Short name T588
Test name
Test status
Simulation time 17248307967 ps
CPU time 163.77 seconds
Started May 23 12:42:37 PM PDT 24
Finished May 23 12:45:22 PM PDT 24
Peak memory 198148 kb
Host smart-de4bea95-e4e2-4ba9-bcea-a8f16d4d1ad8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595094881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.2595094881
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.1029657942
Short name T548
Test name
Test status
Simulation time 11692997 ps
CPU time 0.59 seconds
Started May 23 12:42:49 PM PDT 24
Finished May 23 12:42:52 PM PDT 24
Peak memory 194444 kb
Host smart-cf0e773e-974e-49be-8d90-1b3471d5a7a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029657942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.1029657942
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.1831215133
Short name T590
Test name
Test status
Simulation time 508853602 ps
CPU time 0.74 seconds
Started May 23 12:42:38 PM PDT 24
Finished May 23 12:42:40 PM PDT 24
Peak memory 195164 kb
Host smart-2660e314-3bdb-48c3-9bf4-8669409db490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831215133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.1831215133
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.3560100974
Short name T567
Test name
Test status
Simulation time 167569384 ps
CPU time 5.87 seconds
Started May 23 12:42:50 PM PDT 24
Finished May 23 12:43:00 PM PDT 24
Peak memory 196144 kb
Host smart-56ae1696-d1ea-4e26-bc83-eee6ea0c1265
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560100974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.3560100974
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.3082144093
Short name T195
Test name
Test status
Simulation time 130618186 ps
CPU time 0.81 seconds
Started May 23 12:42:49 PM PDT 24
Finished May 23 12:42:51 PM PDT 24
Peak memory 195688 kb
Host smart-461fd6a6-d3b7-4d4f-a82c-0235a25d5dd3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082144093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.3082144093
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.1384347478
Short name T525
Test name
Test status
Simulation time 137871614 ps
CPU time 1.26 seconds
Started May 23 12:42:52 PM PDT 24
Finished May 23 12:42:56 PM PDT 24
Peak memory 195940 kb
Host smart-f3c1905b-934e-4b29-8c91-8c55cc736b32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384347478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.1384347478
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.2375977284
Short name T83
Test name
Test status
Simulation time 162858075 ps
CPU time 1.91 seconds
Started May 23 12:42:47 PM PDT 24
Finished May 23 12:42:50 PM PDT 24
Peak memory 197924 kb
Host smart-07127a2f-1ad2-45de-8402-2fc7cbc8a963
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375977284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.2375977284
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.1778707879
Short name T216
Test name
Test status
Simulation time 294338768 ps
CPU time 2.98 seconds
Started May 23 12:42:47 PM PDT 24
Finished May 23 12:42:51 PM PDT 24
Peak memory 197204 kb
Host smart-fff40447-5e7a-410b-b1a6-efbd663f1f49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778707879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.1778707879
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.1327736408
Short name T427
Test name
Test status
Simulation time 1012317111 ps
CPU time 1.17 seconds
Started May 23 12:42:30 PM PDT 24
Finished May 23 12:42:32 PM PDT 24
Peak memory 196976 kb
Host smart-b0dbfc63-40c8-40a6-b7dd-6e5332700bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327736408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.1327736408
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.1565490377
Short name T123
Test name
Test status
Simulation time 22508316 ps
CPU time 0.74 seconds
Started May 23 12:42:35 PM PDT 24
Finished May 23 12:42:37 PM PDT 24
Peak memory 195380 kb
Host smart-4bd150bc-e9ac-46d9-b0f3-12c25643f914
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565490377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.1565490377
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_smoke.1985360851
Short name T647
Test name
Test status
Simulation time 148541888 ps
CPU time 1.03 seconds
Started May 23 12:42:31 PM PDT 24
Finished May 23 12:42:33 PM PDT 24
Peak memory 195712 kb
Host smart-bb814f88-b702-4d99-be46-174cd28ae0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985360851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.1985360851
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.2742132254
Short name T350
Test name
Test status
Simulation time 271213316 ps
CPU time 1.31 seconds
Started May 23 12:42:37 PM PDT 24
Finished May 23 12:42:40 PM PDT 24
Peak memory 197824 kb
Host smart-1a3f6b02-2327-4236-9509-0f61e587e532
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742132254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.2742132254
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.3436079926
Short name T153
Test name
Test status
Simulation time 5545766134 ps
CPU time 136.35 seconds
Started May 23 12:42:50 PM PDT 24
Finished May 23 12:45:09 PM PDT 24
Peak memory 198128 kb
Host smart-da8380a1-5102-4338-9b15-3893e8377cc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436079926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.3436079926
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.1490100814
Short name T199
Test name
Test status
Simulation time 76030202 ps
CPU time 0.55 seconds
Started May 23 12:42:47 PM PDT 24
Finished May 23 12:42:49 PM PDT 24
Peak memory 193804 kb
Host smart-c4b9e01e-71a4-4edf-99e3-d16fe4464386
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490100814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.1490100814
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.1097011285
Short name T341
Test name
Test status
Simulation time 87232122 ps
CPU time 0.61 seconds
Started May 23 12:42:47 PM PDT 24
Finished May 23 12:42:48 PM PDT 24
Peak memory 194568 kb
Host smart-1546e0a6-5cc8-455e-9013-3f413c1adefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097011285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.1097011285
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.2351890322
Short name T539
Test name
Test status
Simulation time 424278482 ps
CPU time 10.93 seconds
Started May 23 12:42:49 PM PDT 24
Finished May 23 12:43:02 PM PDT 24
Peak memory 195400 kb
Host smart-2543421f-a2cc-4989-843b-1ec9859f18e0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351890322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.2351890322
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.733264671
Short name T34
Test name
Test status
Simulation time 30508307 ps
CPU time 0.71 seconds
Started May 23 12:42:46 PM PDT 24
Finished May 23 12:42:48 PM PDT 24
Peak memory 195480 kb
Host smart-0fd60a10-6ebb-4e0a-97bf-cba88110a413
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733264671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.733264671
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.3284666456
Short name T187
Test name
Test status
Simulation time 49652231 ps
CPU time 0.72 seconds
Started May 23 12:42:51 PM PDT 24
Finished May 23 12:42:55 PM PDT 24
Peak memory 194392 kb
Host smart-0bd3f722-ad90-4d94-830c-3e695a5ed9a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284666456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.3284666456
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.3318508866
Short name T295
Test name
Test status
Simulation time 170153732 ps
CPU time 3.38 seconds
Started May 23 12:42:49 PM PDT 24
Finished May 23 12:42:55 PM PDT 24
Peak memory 197996 kb
Host smart-10faa4a8-2c51-44a8-829b-906cad8c855f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318508866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.3318508866
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.3219660786
Short name T643
Test name
Test status
Simulation time 354483529 ps
CPU time 2.05 seconds
Started May 23 12:42:49 PM PDT 24
Finished May 23 12:42:52 PM PDT 24
Peak memory 196200 kb
Host smart-25caa28f-703c-4513-9334-2064773531e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219660786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.3219660786
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.366408657
Short name T248
Test name
Test status
Simulation time 47645807 ps
CPU time 0.99 seconds
Started May 23 12:42:48 PM PDT 24
Finished May 23 12:42:51 PM PDT 24
Peak memory 195864 kb
Host smart-31066b7a-a70f-4bad-b9ae-eab01afba077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366408657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.366408657
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.3112875424
Short name T527
Test name
Test status
Simulation time 65975801 ps
CPU time 0.77 seconds
Started May 23 12:42:49 PM PDT 24
Finished May 23 12:42:51 PM PDT 24
Peak memory 196020 kb
Host smart-738fc996-7d9b-4417-944b-64dfc83be8e4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112875424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.3112875424
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.2397783552
Short name T7
Test name
Test status
Simulation time 416755421 ps
CPU time 1.75 seconds
Started May 23 12:42:50 PM PDT 24
Finished May 23 12:42:54 PM PDT 24
Peak memory 197804 kb
Host smart-a992ab7d-1eb1-49e8-b337-131fd3c3b84d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397783552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.2397783552
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.3392285424
Short name T360
Test name
Test status
Simulation time 28654188 ps
CPU time 0.98 seconds
Started May 23 12:42:50 PM PDT 24
Finished May 23 12:42:55 PM PDT 24
Peak memory 196104 kb
Host smart-67944dc9-d45e-4e39-8b87-5b968426e53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392285424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.3392285424
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.2355759929
Short name T150
Test name
Test status
Simulation time 68299484 ps
CPU time 1.14 seconds
Started May 23 12:42:46 PM PDT 24
Finished May 23 12:42:48 PM PDT 24
Peak memory 196204 kb
Host smart-ebb29e9c-e02b-411c-b2f5-2e88fc8d9c04
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355759929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.2355759929
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.3471645505
Short name T423
Test name
Test status
Simulation time 27659444341 ps
CPU time 189.99 seconds
Started May 23 12:42:48 PM PDT 24
Finished May 23 12:45:59 PM PDT 24
Peak memory 198036 kb
Host smart-dcd30bd5-2225-46cb-a1c5-e8e06272022c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471645505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.3471645505
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.4257375786
Short name T443
Test name
Test status
Simulation time 102692478982 ps
CPU time 607.67 seconds
Started May 23 12:42:49 PM PDT 24
Finished May 23 12:52:58 PM PDT 24
Peak memory 198108 kb
Host smart-c43ed3ee-89d1-4d3f-8df2-13f9933ee9f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4257375786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.4257375786
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.2432524785
Short name T46
Test name
Test status
Simulation time 123580606 ps
CPU time 0.56 seconds
Started May 23 12:42:49 PM PDT 24
Finished May 23 12:42:52 PM PDT 24
Peak memory 193772 kb
Host smart-7dfaf1e1-2b01-489a-92f8-a67360c1a085
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432524785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.2432524785
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.257342590
Short name T32
Test name
Test status
Simulation time 63679974 ps
CPU time 0.61 seconds
Started May 23 12:42:49 PM PDT 24
Finished May 23 12:42:52 PM PDT 24
Peak memory 194068 kb
Host smart-d52e4ebb-f6c8-4a6f-a85e-d93f1ca88801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257342590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.257342590
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.1885280249
Short name T691
Test name
Test status
Simulation time 652054230 ps
CPU time 21.06 seconds
Started May 23 12:42:48 PM PDT 24
Finished May 23 12:43:11 PM PDT 24
Peak memory 196796 kb
Host smart-ae1ab8e4-6bf4-4ba4-a1f1-5ea87768ddab
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885280249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.1885280249
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.887110347
Short name T355
Test name
Test status
Simulation time 72406314 ps
CPU time 0.65 seconds
Started May 23 12:42:47 PM PDT 24
Finished May 23 12:42:49 PM PDT 24
Peak memory 194384 kb
Host smart-c2de2ea4-c94f-4558-8a90-7a5724ecc892
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887110347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.887110347
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.3656327521
Short name T224
Test name
Test status
Simulation time 32141021 ps
CPU time 0.71 seconds
Started May 23 12:42:52 PM PDT 24
Finished May 23 12:42:56 PM PDT 24
Peak memory 194312 kb
Host smart-094461cf-39d1-48b8-aa5f-1e9dcd11d242
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656327521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.3656327521
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.2695817553
Short name T226
Test name
Test status
Simulation time 65243811 ps
CPU time 2.73 seconds
Started May 23 12:42:47 PM PDT 24
Finished May 23 12:42:51 PM PDT 24
Peak memory 196320 kb
Host smart-3bfd1320-d1de-40e5-bbfd-2dcbf21ba87d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695817553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.2695817553
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.1552927433
Short name T665
Test name
Test status
Simulation time 55139263 ps
CPU time 1.25 seconds
Started May 23 12:42:51 PM PDT 24
Finished May 23 12:42:55 PM PDT 24
Peak memory 195672 kb
Host smart-ad0fd1fb-8f7f-4e89-a3a8-6fa0aa84c198
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552927433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.1552927433
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.3250583933
Short name T597
Test name
Test status
Simulation time 53053329 ps
CPU time 1.13 seconds
Started May 23 12:42:57 PM PDT 24
Finished May 23 12:43:00 PM PDT 24
Peak memory 195692 kb
Host smart-3b49fb78-d2c7-47a8-ad43-da9b89723849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250583933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.3250583933
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.955693246
Short name T508
Test name
Test status
Simulation time 53267131 ps
CPU time 1.29 seconds
Started May 23 12:42:50 PM PDT 24
Finished May 23 12:42:54 PM PDT 24
Peak memory 197012 kb
Host smart-1bf4c032-a6a7-49bc-952e-f8cc6d7fefdc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955693246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup
_pulldown.955693246
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.4078827242
Short name T496
Test name
Test status
Simulation time 305738303 ps
CPU time 5.11 seconds
Started May 23 12:42:47 PM PDT 24
Finished May 23 12:42:53 PM PDT 24
Peak memory 197868 kb
Host smart-2615d67f-4278-4a3b-9b5c-4f75a6f71153
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078827242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.4078827242
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.3271247979
Short name T19
Test name
Test status
Simulation time 86665799 ps
CPU time 1.22 seconds
Started May 23 12:42:44 PM PDT 24
Finished May 23 12:42:46 PM PDT 24
Peak memory 196860 kb
Host smart-5a8cff79-de17-402d-8e56-25fce157d8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271247979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.3271247979
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.106049902
Short name T624
Test name
Test status
Simulation time 126765400 ps
CPU time 0.91 seconds
Started May 23 12:42:46 PM PDT 24
Finished May 23 12:42:48 PM PDT 24
Peak memory 196332 kb
Host smart-15b75bf0-c4f5-452a-a5b4-929d11191ed5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106049902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.106049902
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.3526483831
Short name T603
Test name
Test status
Simulation time 18954752053 ps
CPU time 193.55 seconds
Started May 23 12:42:58 PM PDT 24
Finished May 23 12:46:13 PM PDT 24
Peak memory 198088 kb
Host smart-fb3f5772-009b-42bf-915f-79f0a88024f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526483831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.3526483831
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.1331075428
Short name T374
Test name
Test status
Simulation time 24952032 ps
CPU time 0.55 seconds
Started May 23 12:42:49 PM PDT 24
Finished May 23 12:42:51 PM PDT 24
Peak memory 193804 kb
Host smart-fbec5542-7ddf-406f-bf23-983e8bd6d098
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331075428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.1331075428
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.1993865119
Short name T400
Test name
Test status
Simulation time 28707489 ps
CPU time 0.68 seconds
Started May 23 12:42:48 PM PDT 24
Finished May 23 12:42:50 PM PDT 24
Peak memory 194012 kb
Host smart-5a4f997d-ce24-4386-b5c6-b4db5b5021ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993865119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.1993865119
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.995895364
Short name T612
Test name
Test status
Simulation time 1610270525 ps
CPU time 15.82 seconds
Started May 23 12:42:49 PM PDT 24
Finished May 23 12:43:06 PM PDT 24
Peak memory 197792 kb
Host smart-dfe8eb9a-6b37-4264-8fe4-0657471536c4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995895364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stres
s.995895364
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.2087013565
Short name T700
Test name
Test status
Simulation time 249069690 ps
CPU time 1 seconds
Started May 23 12:42:51 PM PDT 24
Finished May 23 12:42:55 PM PDT 24
Peak memory 196044 kb
Host smart-ba1e76bf-bb29-45ab-949b-a9958c2d9fc8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087013565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.2087013565
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.970338545
Short name T309
Test name
Test status
Simulation time 101260037 ps
CPU time 1.11 seconds
Started May 23 12:42:52 PM PDT 24
Finished May 23 12:42:56 PM PDT 24
Peak memory 196576 kb
Host smart-e3500e19-8da4-46e9-af98-bd8133cfc9c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970338545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.970338545
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.530318963
Short name T535
Test name
Test status
Simulation time 45977911 ps
CPU time 1.95 seconds
Started May 23 12:42:49 PM PDT 24
Finished May 23 12:42:53 PM PDT 24
Peak memory 197984 kb
Host smart-4fe31f51-0d8c-4bda-bdfb-cf08c1ba168d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530318963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.gpio_intr_with_filter_rand_intr_event.530318963
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.1116864056
Short name T285
Test name
Test status
Simulation time 170106400 ps
CPU time 3.18 seconds
Started May 23 12:42:52 PM PDT 24
Finished May 23 12:42:58 PM PDT 24
Peak memory 197268 kb
Host smart-f96b9ca2-483b-4c4d-98a8-86378c7b6495
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116864056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.1116864056
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.1053005120
Short name T117
Test name
Test status
Simulation time 80683264 ps
CPU time 1.06 seconds
Started May 23 12:42:50 PM PDT 24
Finished May 23 12:42:53 PM PDT 24
Peak memory 196476 kb
Host smart-4f5fe8c3-5a50-44a8-a26b-db15f1570977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053005120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.1053005120
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.3211937427
Short name T154
Test name
Test status
Simulation time 52530085 ps
CPU time 0.75 seconds
Started May 23 12:42:51 PM PDT 24
Finished May 23 12:42:55 PM PDT 24
Peak memory 196036 kb
Host smart-d2bd2b6b-cc9a-4281-a8fb-03a34d68a811
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211937427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.3211937427
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.2724692859
Short name T211
Test name
Test status
Simulation time 92296170 ps
CPU time 3.81 seconds
Started May 23 12:42:50 PM PDT 24
Finished May 23 12:42:56 PM PDT 24
Peak memory 197704 kb
Host smart-bbe8e574-079c-4016-bb55-001e790d1522
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724692859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.2724692859
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.1035115054
Short name T595
Test name
Test status
Simulation time 65603011 ps
CPU time 1.17 seconds
Started May 23 12:42:54 PM PDT 24
Finished May 23 12:42:58 PM PDT 24
Peak memory 195624 kb
Host smart-e21ce1f2-f53b-451a-9ef5-ca8bf9fffe2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035115054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.1035115054
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.2234763854
Short name T180
Test name
Test status
Simulation time 67076698 ps
CPU time 1.18 seconds
Started May 23 12:42:48 PM PDT 24
Finished May 23 12:42:51 PM PDT 24
Peak memory 195592 kb
Host smart-9f62be95-39b0-4cee-aadd-00ba7a372d24
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234763854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.2234763854
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.213902247
Short name T25
Test name
Test status
Simulation time 7777784296 ps
CPU time 108.68 seconds
Started May 23 12:42:52 PM PDT 24
Finished May 23 12:44:44 PM PDT 24
Peak memory 198052 kb
Host smart-5dab59fb-9bac-4536-a8dc-211e993bc4a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213902247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.g
pio_stress_all.213902247
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.3548843959
Short name T497
Test name
Test status
Simulation time 16173909522 ps
CPU time 297.27 seconds
Started May 23 12:42:52 PM PDT 24
Finished May 23 12:47:52 PM PDT 24
Peak memory 198180 kb
Host smart-c0eef1a9-70af-4856-8f39-978bba1063c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3548843959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.3548843959
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.1512737109
Short name T607
Test name
Test status
Simulation time 26599198 ps
CPU time 0.57 seconds
Started May 23 12:42:55 PM PDT 24
Finished May 23 12:42:58 PM PDT 24
Peak memory 194464 kb
Host smart-bc607e16-daef-468e-b087-ecc8933eb480
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512737109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.1512737109
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.2604599893
Short name T522
Test name
Test status
Simulation time 370789089 ps
CPU time 0.84 seconds
Started May 23 12:42:50 PM PDT 24
Finished May 23 12:42:55 PM PDT 24
Peak memory 196028 kb
Host smart-f4ca4f58-1b0e-434b-aa37-6774a50b8336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604599893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.2604599893
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.3011514735
Short name T516
Test name
Test status
Simulation time 1395658716 ps
CPU time 14.43 seconds
Started May 23 12:42:52 PM PDT 24
Finished May 23 12:43:10 PM PDT 24
Peak memory 196600 kb
Host smart-2ac8cb63-e3bd-4dad-9d1a-db4ba4fc0cdb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011514735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.3011514735
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.3025630516
Short name T20
Test name
Test status
Simulation time 367190928 ps
CPU time 0.93 seconds
Started May 23 12:42:51 PM PDT 24
Finished May 23 12:42:55 PM PDT 24
Peak memory 195984 kb
Host smart-277d493c-045b-47f9-9bbf-45e2a12aa9d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025630516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.3025630516
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.467978488
Short name T475
Test name
Test status
Simulation time 38904627 ps
CPU time 0.89 seconds
Started May 23 12:42:49 PM PDT 24
Finished May 23 12:42:52 PM PDT 24
Peak memory 197140 kb
Host smart-12a3fd15-7d48-4702-8d64-278deba69345
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467978488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.467978488
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.3760301000
Short name T670
Test name
Test status
Simulation time 65425729 ps
CPU time 2.49 seconds
Started May 23 12:42:51 PM PDT 24
Finished May 23 12:42:57 PM PDT 24
Peak memory 197980 kb
Host smart-9bfaf1de-6a1a-4cd6-881f-123e766e11ba
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760301000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.3760301000
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.550474013
Short name T205
Test name
Test status
Simulation time 418621374 ps
CPU time 3.13 seconds
Started May 23 12:42:50 PM PDT 24
Finished May 23 12:42:57 PM PDT 24
Peak memory 195684 kb
Host smart-c2cc1963-ad6d-4442-9cd0-1defd9a70030
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550474013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger.
550474013
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.2265048119
Short name T250
Test name
Test status
Simulation time 351195899 ps
CPU time 1.26 seconds
Started May 23 12:42:49 PM PDT 24
Finished May 23 12:42:51 PM PDT 24
Peak memory 195756 kb
Host smart-2419a0d2-6bbe-4296-a723-2f4335e38300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265048119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.2265048119
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.157025264
Short name T311
Test name
Test status
Simulation time 20157693 ps
CPU time 0.74 seconds
Started May 23 12:42:52 PM PDT 24
Finished May 23 12:42:56 PM PDT 24
Peak memory 195452 kb
Host smart-abc99875-59c8-4f4e-82b6-a536f4d0cef4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157025264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullup
_pulldown.157025264
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.3823544652
Short name T266
Test name
Test status
Simulation time 459803862 ps
CPU time 4.71 seconds
Started May 23 12:42:51 PM PDT 24
Finished May 23 12:42:59 PM PDT 24
Peak memory 197836 kb
Host smart-83dee1cc-6698-46c5-9746-11c2c46e58fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823544652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.3823544652
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.407324835
Short name T247
Test name
Test status
Simulation time 51529846 ps
CPU time 1.38 seconds
Started May 23 12:42:50 PM PDT 24
Finished May 23 12:42:55 PM PDT 24
Peak memory 195384 kb
Host smart-08a0179f-ee57-45f1-8f32-acf8369c956b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407324835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.407324835
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.4075192862
Short name T512
Test name
Test status
Simulation time 71724396 ps
CPU time 0.77 seconds
Started May 23 12:42:49 PM PDT 24
Finished May 23 12:42:51 PM PDT 24
Peak memory 195768 kb
Host smart-53386020-b44c-4332-b4b6-51e4769974af
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075192862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.4075192862
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.1024019669
Short name T466
Test name
Test status
Simulation time 2089141546 ps
CPU time 56.99 seconds
Started May 23 12:42:55 PM PDT 24
Finished May 23 12:43:54 PM PDT 24
Peak memory 197352 kb
Host smart-77845fd1-40d4-4cf2-abbe-82eaf7383645
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024019669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.1024019669
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.581316534
Short name T354
Test name
Test status
Simulation time 15115632 ps
CPU time 0.63 seconds
Started May 23 12:42:53 PM PDT 24
Finished May 23 12:42:57 PM PDT 24
Peak memory 193860 kb
Host smart-f5ebe587-9fe1-4ac1-a6f5-d6909759cdea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581316534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.581316534
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.2686822475
Short name T259
Test name
Test status
Simulation time 39419349 ps
CPU time 0.91 seconds
Started May 23 12:42:52 PM PDT 24
Finished May 23 12:42:57 PM PDT 24
Peak memory 196440 kb
Host smart-0b29e70c-cf26-4103-86f1-275e915b7a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686822475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.2686822475
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.2240179714
Short name T171
Test name
Test status
Simulation time 1705574073 ps
CPU time 11.6 seconds
Started May 23 12:42:55 PM PDT 24
Finished May 23 12:43:09 PM PDT 24
Peak memory 195360 kb
Host smart-b06a292e-f0b6-44d1-b319-071c5a7ad55f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240179714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.2240179714
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.2392037084
Short name T578
Test name
Test status
Simulation time 289232794 ps
CPU time 0.95 seconds
Started May 23 12:42:55 PM PDT 24
Finished May 23 12:42:58 PM PDT 24
Peak memory 196636 kb
Host smart-2b1294cd-b342-4dc2-bb57-fdb5e259d867
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392037084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.2392037084
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.3688965760
Short name T236
Test name
Test status
Simulation time 69342775 ps
CPU time 0.7 seconds
Started May 23 12:42:52 PM PDT 24
Finished May 23 12:42:56 PM PDT 24
Peak memory 194928 kb
Host smart-8eedf716-abd5-4ed2-b097-ffa301041ba9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688965760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.3688965760
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.416050977
Short name T189
Test name
Test status
Simulation time 43410742 ps
CPU time 1.93 seconds
Started May 23 12:42:52 PM PDT 24
Finished May 23 12:42:58 PM PDT 24
Peak memory 197932 kb
Host smart-ded0c6b8-23f5-41dc-b70c-29e1add41c18
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416050977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.gpio_intr_with_filter_rand_intr_event.416050977
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.3023699888
Short name T292
Test name
Test status
Simulation time 130599769 ps
CPU time 2.87 seconds
Started May 23 12:42:53 PM PDT 24
Finished May 23 12:42:59 PM PDT 24
Peak memory 197896 kb
Host smart-b6c9aa5f-740c-4a75-8f46-c5bc4a1eb9eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023699888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.3023699888
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.441244718
Short name T654
Test name
Test status
Simulation time 168855820 ps
CPU time 1.06 seconds
Started May 23 12:42:54 PM PDT 24
Finished May 23 12:42:58 PM PDT 24
Peak memory 195888 kb
Host smart-2cedad6b-7742-4a87-a8f1-2b950b64d783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441244718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.441244718
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.844271911
Short name T559
Test name
Test status
Simulation time 26772911 ps
CPU time 0.78 seconds
Started May 23 12:42:55 PM PDT 24
Finished May 23 12:42:58 PM PDT 24
Peak memory 195364 kb
Host smart-850f630f-86b6-42b2-a22b-ee3873139275
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844271911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullup
_pulldown.844271911
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.1129364624
Short name T614
Test name
Test status
Simulation time 109060792 ps
CPU time 5.19 seconds
Started May 23 12:42:52 PM PDT 24
Finished May 23 12:43:01 PM PDT 24
Peak memory 197840 kb
Host smart-a6cd43cd-e4f7-4f40-895d-ad9c85f65b0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129364624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.1129364624
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.1534075587
Short name T185
Test name
Test status
Simulation time 180421817 ps
CPU time 1.4 seconds
Started May 23 12:42:51 PM PDT 24
Finished May 23 12:42:56 PM PDT 24
Peak memory 196612 kb
Host smart-5cf68022-1035-4f15-bd3a-f2923951c9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534075587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.1534075587
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.2615312835
Short name T192
Test name
Test status
Simulation time 89535803 ps
CPU time 1.22 seconds
Started May 23 12:42:47 PM PDT 24
Finished May 23 12:42:49 PM PDT 24
Peak memory 196788 kb
Host smart-3065889c-b46e-488f-901a-d3c177ff1fb8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615312835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.2615312835
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.2090945239
Short name T626
Test name
Test status
Simulation time 30943454257 ps
CPU time 160.7 seconds
Started May 23 12:42:53 PM PDT 24
Finished May 23 12:45:37 PM PDT 24
Peak memory 198108 kb
Host smart-ec873aa7-43c5-4dbb-bbdb-a5cf9be68278
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090945239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.2090945239
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.3558806043
Short name T683
Test name
Test status
Simulation time 26655911 ps
CPU time 0.59 seconds
Started May 23 12:43:01 PM PDT 24
Finished May 23 12:43:03 PM PDT 24
Peak memory 193848 kb
Host smart-b7e46110-9fc7-480d-81f2-6537ab300c0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558806043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.3558806043
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.359805365
Short name T467
Test name
Test status
Simulation time 47787576 ps
CPU time 0.67 seconds
Started May 23 12:43:04 PM PDT 24
Finished May 23 12:43:07 PM PDT 24
Peak memory 194068 kb
Host smart-ae8e6806-4f39-4ec6-b0fb-e5aea4697b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359805365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.359805365
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.3442306404
Short name T35
Test name
Test status
Simulation time 627128600 ps
CPU time 10 seconds
Started May 23 12:43:07 PM PDT 24
Finished May 23 12:43:21 PM PDT 24
Peak memory 197796 kb
Host smart-72553a60-1fa1-4885-b319-595c6155f052
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442306404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.3442306404
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.2921249544
Short name T177
Test name
Test status
Simulation time 195412611 ps
CPU time 0.78 seconds
Started May 23 12:43:04 PM PDT 24
Finished May 23 12:43:07 PM PDT 24
Peak memory 195780 kb
Host smart-d0b318f2-2813-4b64-b71e-295f54f1da27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921249544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.2921249544
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.1979882735
Short name T225
Test name
Test status
Simulation time 509111647 ps
CPU time 1.23 seconds
Started May 23 12:43:07 PM PDT 24
Finished May 23 12:43:12 PM PDT 24
Peak memory 197104 kb
Host smart-5196ed9b-0e57-47a0-b9c3-3e86442cd06b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979882735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.1979882735
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.4141098411
Short name T576
Test name
Test status
Simulation time 515835128 ps
CPU time 2.72 seconds
Started May 23 12:43:03 PM PDT 24
Finished May 23 12:43:07 PM PDT 24
Peak memory 197940 kb
Host smart-7b5b64dd-be93-4b53-a724-e8f89f1da7aa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141098411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.4141098411
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.2213591689
Short name T318
Test name
Test status
Simulation time 106016883 ps
CPU time 2.35 seconds
Started May 23 12:43:07 PM PDT 24
Finished May 23 12:43:12 PM PDT 24
Peak memory 195972 kb
Host smart-e8965432-8d60-464c-815a-24d72a5a6f93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213591689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.2213591689
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.3108624189
Short name T116
Test name
Test status
Simulation time 117989446 ps
CPU time 1.07 seconds
Started May 23 12:43:03 PM PDT 24
Finished May 23 12:43:06 PM PDT 24
Peak memory 195816 kb
Host smart-84ba56ae-a0a9-4761-b012-31f813da7c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108624189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.3108624189
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.1924450688
Short name T287
Test name
Test status
Simulation time 35073885 ps
CPU time 1.18 seconds
Started May 23 12:43:04 PM PDT 24
Finished May 23 12:43:07 PM PDT 24
Peak memory 196984 kb
Host smart-67337179-2b47-437a-bc73-01c7e60b2271
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924450688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.1924450688
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.2293498669
Short name T141
Test name
Test status
Simulation time 102522468 ps
CPU time 1.17 seconds
Started May 23 12:43:07 PM PDT 24
Finished May 23 12:43:11 PM PDT 24
Peak memory 197868 kb
Host smart-abb9f7f4-b63a-468b-9beb-ed3405efdee3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293498669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.2293498669
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.419606613
Short name T370
Test name
Test status
Simulation time 65092648 ps
CPU time 1.23 seconds
Started May 23 12:42:53 PM PDT 24
Finished May 23 12:42:58 PM PDT 24
Peak memory 196300 kb
Host smart-268c0f67-0acd-4188-87ce-14fd5009ef4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419606613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.419606613
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.2976079446
Short name T202
Test name
Test status
Simulation time 25875287 ps
CPU time 0.83 seconds
Started May 23 12:43:08 PM PDT 24
Finished May 23 12:43:12 PM PDT 24
Peak memory 195176 kb
Host smart-fdc2f277-b998-49f1-8c49-b72e83b61baa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976079446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.2976079446
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.1848551674
Short name T277
Test name
Test status
Simulation time 24152016657 ps
CPU time 58.59 seconds
Started May 23 12:43:07 PM PDT 24
Finished May 23 12:44:09 PM PDT 24
Peak memory 198016 kb
Host smart-724afbb4-1394-4837-9882-33e2c65f0ed8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848551674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.1848551674
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.4069692949
Short name T487
Test name
Test status
Simulation time 40713190 ps
CPU time 0.61 seconds
Started May 23 12:43:24 PM PDT 24
Finished May 23 12:43:27 PM PDT 24
Peak memory 193776 kb
Host smart-9af4ac35-e48c-4980-a571-aaf1448be716
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069692949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.4069692949
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.1678545215
Short name T304
Test name
Test status
Simulation time 71869535 ps
CPU time 0.72 seconds
Started May 23 12:43:07 PM PDT 24
Finished May 23 12:43:11 PM PDT 24
Peak memory 195188 kb
Host smart-4b11c77a-de05-4a79-b024-2ae1ac94852b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678545215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.1678545215
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.3446423378
Short name T62
Test name
Test status
Simulation time 431661552 ps
CPU time 21.7 seconds
Started May 23 12:43:08 PM PDT 24
Finished May 23 12:43:33 PM PDT 24
Peak memory 195448 kb
Host smart-97566c87-3b10-4c26-9a0e-b94f566af0ff
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446423378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.3446423378
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.890757836
Short name T608
Test name
Test status
Simulation time 46357071 ps
CPU time 0.78 seconds
Started May 23 12:43:08 PM PDT 24
Finished May 23 12:43:12 PM PDT 24
Peak memory 195836 kb
Host smart-4ccba9ee-7f3e-4632-a793-549c14f4d12c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890757836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.890757836
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.2990536886
Short name T474
Test name
Test status
Simulation time 25654643 ps
CPU time 0.69 seconds
Started May 23 12:43:04 PM PDT 24
Finished May 23 12:43:07 PM PDT 24
Peak memory 195096 kb
Host smart-66dda87a-7180-42af-b7bf-93029af3dfff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990536886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.2990536886
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.2215968551
Short name T263
Test name
Test status
Simulation time 42236498 ps
CPU time 1.79 seconds
Started May 23 12:43:08 PM PDT 24
Finished May 23 12:43:13 PM PDT 24
Peak memory 197892 kb
Host smart-8d3f4fde-9706-45fa-a0e4-8535033ae2d8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215968551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.2215968551
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.3085473223
Short name T450
Test name
Test status
Simulation time 633214570 ps
CPU time 2.2 seconds
Started May 23 12:43:03 PM PDT 24
Finished May 23 12:43:06 PM PDT 24
Peak memory 195848 kb
Host smart-20765af8-0ed4-4d53-a48d-708f5ccfa9a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085473223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.3085473223
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.1970327982
Short name T383
Test name
Test status
Simulation time 65008785 ps
CPU time 1.25 seconds
Started May 23 12:43:03 PM PDT 24
Finished May 23 12:43:06 PM PDT 24
Peak memory 196984 kb
Host smart-bcf55523-d693-448a-ad7b-fbdb785d190f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970327982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.1970327982
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.3049074306
Short name T482
Test name
Test status
Simulation time 614275416 ps
CPU time 0.92 seconds
Started May 23 12:43:03 PM PDT 24
Finished May 23 12:43:06 PM PDT 24
Peak memory 195916 kb
Host smart-52c883ed-121b-43e9-a992-3eee8d3f2337
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049074306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.3049074306
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.372627514
Short name T498
Test name
Test status
Simulation time 112307255 ps
CPU time 5.02 seconds
Started May 23 12:43:01 PM PDT 24
Finished May 23 12:43:07 PM PDT 24
Peak memory 197756 kb
Host smart-f97355c8-58b4-4960-a556-9c8e94e5890f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372627514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ran
dom_long_reg_writes_reg_reads.372627514
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.3758197038
Short name T353
Test name
Test status
Simulation time 44898455 ps
CPU time 1.24 seconds
Started May 23 12:43:09 PM PDT 24
Finished May 23 12:43:13 PM PDT 24
Peak memory 196508 kb
Host smart-15511575-99c4-4078-9b14-d7072443560d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758197038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.3758197038
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.1676000871
Short name T126
Test name
Test status
Simulation time 86592786 ps
CPU time 1.07 seconds
Started May 23 12:43:05 PM PDT 24
Finished May 23 12:43:09 PM PDT 24
Peak memory 196372 kb
Host smart-46198a57-8082-414d-b703-c562cf4dff8f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676000871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.1676000871
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.2268515430
Short name T671
Test name
Test status
Simulation time 7578913448 ps
CPU time 115.88 seconds
Started May 23 12:43:02 PM PDT 24
Finished May 23 12:44:59 PM PDT 24
Peak memory 198044 kb
Host smart-0a129cd1-8efd-4b90-a532-43d8a0908003
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268515430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.2268515430
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.181172557
Short name T471
Test name
Test status
Simulation time 18759284 ps
CPU time 0.56 seconds
Started May 23 12:41:51 PM PDT 24
Finished May 23 12:41:54 PM PDT 24
Peak memory 193808 kb
Host smart-af3062e2-7a76-42a9-9756-dd3969ce8b64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181172557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.181172557
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.255794588
Short name T138
Test name
Test status
Simulation time 35255075 ps
CPU time 0.88 seconds
Started May 23 12:41:52 PM PDT 24
Finished May 23 12:41:55 PM PDT 24
Peak memory 196060 kb
Host smart-5eeee573-5365-4f03-b863-8a16faf551c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255794588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.255794588
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.3791498094
Short name T470
Test name
Test status
Simulation time 233911564 ps
CPU time 5.78 seconds
Started May 23 12:41:50 PM PDT 24
Finished May 23 12:41:57 PM PDT 24
Peak memory 195384 kb
Host smart-880a63c5-366e-4d33-8d2b-5118636c5179
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791498094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.3791498094
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.3812972662
Short name T357
Test name
Test status
Simulation time 60566927 ps
CPU time 0.66 seconds
Started May 23 12:41:50 PM PDT 24
Finished May 23 12:41:53 PM PDT 24
Peak memory 194636 kb
Host smart-0a54514a-7e89-4837-b399-3dd9fa784575
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812972662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.3812972662
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.1414614296
Short name T628
Test name
Test status
Simulation time 39339563 ps
CPU time 1.11 seconds
Started May 23 12:41:50 PM PDT 24
Finished May 23 12:41:53 PM PDT 24
Peak memory 196028 kb
Host smart-4a82c38a-8c32-489b-9fe5-acc3115edcd1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414614296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.1414614296
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.83603245
Short name T155
Test name
Test status
Simulation time 101785370 ps
CPU time 2.18 seconds
Started May 23 12:41:51 PM PDT 24
Finished May 23 12:41:56 PM PDT 24
Peak memory 197840 kb
Host smart-7091a61e-0c34-42b7-981c-491ac476c7a7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83603245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 3.gpio_intr_with_filter_rand_intr_event.83603245
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.2669263434
Short name T611
Test name
Test status
Simulation time 486391628 ps
CPU time 1.07 seconds
Started May 23 12:41:50 PM PDT 24
Finished May 23 12:41:54 PM PDT 24
Peak memory 196036 kb
Host smart-ac94a9f7-66d3-40ad-be6e-dcd9e8599e95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669263434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
2669263434
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.4062662439
Short name T168
Test name
Test status
Simulation time 42993220 ps
CPU time 1.04 seconds
Started May 23 12:41:50 PM PDT 24
Finished May 23 12:41:52 PM PDT 24
Peak memory 195840 kb
Host smart-d118eb22-08d9-41d0-9e97-d9cc853ffdcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062662439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.4062662439
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.903356150
Short name T598
Test name
Test status
Simulation time 159623043 ps
CPU time 1.09 seconds
Started May 23 12:41:46 PM PDT 24
Finished May 23 12:41:47 PM PDT 24
Peak memory 195912 kb
Host smart-5b2b89ec-dc45-4402-b75d-6481f1bbbe4c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903356150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup_
pulldown.903356150
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.360158907
Short name T145
Test name
Test status
Simulation time 618428302 ps
CPU time 2.39 seconds
Started May 23 12:41:51 PM PDT 24
Finished May 23 12:41:56 PM PDT 24
Peak memory 197808 kb
Host smart-162e3dee-57f8-46ce-b79b-580fe93a5b83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360158907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand
om_long_reg_writes_reg_reads.360158907
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_smoke.1789748381
Short name T610
Test name
Test status
Simulation time 174242754 ps
CPU time 1.01 seconds
Started May 23 12:41:50 PM PDT 24
Finished May 23 12:41:52 PM PDT 24
Peak memory 196448 kb
Host smart-bff266c4-a876-4c72-bd46-eec7d49c86bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789748381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.1789748381
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.629104873
Short name T409
Test name
Test status
Simulation time 69834735 ps
CPU time 0.74 seconds
Started May 23 12:41:49 PM PDT 24
Finished May 23 12:41:51 PM PDT 24
Peak memory 195188 kb
Host smart-d642fb37-0d12-4e7b-a40b-056eaf387ba4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629104873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.629104873
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.2810588851
Short name T305
Test name
Test status
Simulation time 6155442759 ps
CPU time 84.32 seconds
Started May 23 12:41:48 PM PDT 24
Finished May 23 12:43:14 PM PDT 24
Peak memory 198132 kb
Host smart-a3029f0b-3b67-4cea-8b70-b1eb149e069b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810588851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.2810588851
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.4212809023
Short name T541
Test name
Test status
Simulation time 33044198699 ps
CPU time 355.36 seconds
Started May 23 12:41:49 PM PDT 24
Finished May 23 12:47:47 PM PDT 24
Peak memory 198168 kb
Host smart-fb79270f-1f8c-4832-87f4-085cc7094e46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4212809023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.4212809023
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.1622741652
Short name T519
Test name
Test status
Simulation time 18004097 ps
CPU time 0.6 seconds
Started May 23 12:43:09 PM PDT 24
Finished May 23 12:43:13 PM PDT 24
Peak memory 193980 kb
Host smart-8971fbd5-dde7-41f5-a8ac-79f359e1950b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622741652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.1622741652
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.1879916500
Short name T636
Test name
Test status
Simulation time 179809247 ps
CPU time 0.8 seconds
Started May 23 12:43:04 PM PDT 24
Finished May 23 12:43:07 PM PDT 24
Peak memory 195136 kb
Host smart-740a5e56-4ff1-44db-9b0c-f5d5b09998a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879916500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.1879916500
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.2534875109
Short name T645
Test name
Test status
Simulation time 489253071 ps
CPU time 14.56 seconds
Started May 23 12:43:07 PM PDT 24
Finished May 23 12:43:25 PM PDT 24
Peak memory 197852 kb
Host smart-5466bc60-15ad-446a-9fcb-489fe5dbcf0d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534875109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.2534875109
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.3240309692
Short name T330
Test name
Test status
Simulation time 1229867256 ps
CPU time 1.07 seconds
Started May 23 12:43:03 PM PDT 24
Finished May 23 12:43:06 PM PDT 24
Peak memory 197688 kb
Host smart-714b12c4-9515-48b0-8d72-4405ef351102
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240309692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.3240309692
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.3739785857
Short name T324
Test name
Test status
Simulation time 235141428 ps
CPU time 0.98 seconds
Started May 23 12:43:02 PM PDT 24
Finished May 23 12:43:05 PM PDT 24
Peak memory 195668 kb
Host smart-ca76b486-beed-40d4-967f-6b39de05c531
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739785857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.3739785857
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.3560279573
Short name T699
Test name
Test status
Simulation time 586343770 ps
CPU time 3.02 seconds
Started May 23 12:43:03 PM PDT 24
Finished May 23 12:43:07 PM PDT 24
Peak memory 197924 kb
Host smart-e9dd6dde-ac28-479f-b8a4-f4f7fd010c71
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560279573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.3560279573
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.1539417121
Short name T536
Test name
Test status
Simulation time 1316768954 ps
CPU time 2.83 seconds
Started May 23 12:43:05 PM PDT 24
Finished May 23 12:43:10 PM PDT 24
Peak memory 195748 kb
Host smart-ebd737c7-b95b-4be2-a3d0-fa0716256b53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539417121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.1539417121
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.507714757
Short name T448
Test name
Test status
Simulation time 94552500 ps
CPU time 1.03 seconds
Started May 23 12:43:01 PM PDT 24
Finished May 23 12:43:03 PM PDT 24
Peak memory 195748 kb
Host smart-b94ac1b4-45f6-415b-868d-f280f05135d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507714757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.507714757
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.1492533123
Short name T476
Test name
Test status
Simulation time 241210077 ps
CPU time 1.23 seconds
Started May 23 12:43:04 PM PDT 24
Finished May 23 12:43:08 PM PDT 24
Peak memory 196856 kb
Host smart-28627514-85e5-43d9-ab83-e79958f5478f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492533123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.1492533123
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.352948507
Short name T702
Test name
Test status
Simulation time 414195610 ps
CPU time 1.82 seconds
Started May 23 12:43:03 PM PDT 24
Finished May 23 12:43:07 PM PDT 24
Peak memory 197868 kb
Host smart-dbba106e-3c79-41db-aad6-a85817be0a2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352948507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ran
dom_long_reg_writes_reg_reads.352948507
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.453867351
Short name T323
Test name
Test status
Simulation time 55767459 ps
CPU time 1.43 seconds
Started May 23 12:43:09 PM PDT 24
Finished May 23 12:43:13 PM PDT 24
Peak memory 197796 kb
Host smart-c152c9c4-02f8-4a9a-a825-4d9cb8d35393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453867351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.453867351
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.2801455707
Short name T709
Test name
Test status
Simulation time 65405992 ps
CPU time 0.93 seconds
Started May 23 12:43:05 PM PDT 24
Finished May 23 12:43:09 PM PDT 24
Peak memory 196432 kb
Host smart-30848051-b7c6-4052-901b-ebd9a4726342
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801455707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.2801455707
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.3799850501
Short name T306
Test name
Test status
Simulation time 14269615012 ps
CPU time 202.35 seconds
Started May 23 12:43:03 PM PDT 24
Finished May 23 12:46:27 PM PDT 24
Peak memory 197972 kb
Host smart-720ee398-e250-4a8b-9004-e92e43e5a24c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799850501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.3799850501
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.1913985296
Short name T622
Test name
Test status
Simulation time 12679654 ps
CPU time 0.56 seconds
Started May 23 12:43:12 PM PDT 24
Finished May 23 12:43:14 PM PDT 24
Peak memory 194672 kb
Host smart-ed289d35-fade-490e-85e2-c7c26a0912db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913985296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.1913985296
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.3204148000
Short name T191
Test name
Test status
Simulation time 90373839 ps
CPU time 0.95 seconds
Started May 23 12:43:04 PM PDT 24
Finished May 23 12:43:07 PM PDT 24
Peak memory 196568 kb
Host smart-12b82184-2d9c-4dd7-85d5-9153aa7348bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204148000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.3204148000
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.3601506989
Short name T333
Test name
Test status
Simulation time 1461602050 ps
CPU time 13.97 seconds
Started May 23 12:43:07 PM PDT 24
Finished May 23 12:43:24 PM PDT 24
Peak memory 197888 kb
Host smart-8530e7ec-366c-4362-be10-f8e06de02dda
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601506989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.3601506989
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.2811030048
Short name T493
Test name
Test status
Simulation time 26942684 ps
CPU time 0.66 seconds
Started May 23 12:43:04 PM PDT 24
Finished May 23 12:43:07 PM PDT 24
Peak memory 194524 kb
Host smart-9f74d8a5-9f32-4b26-80d3-3f70392be5cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811030048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.2811030048
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.2016072406
Short name T387
Test name
Test status
Simulation time 144502405 ps
CPU time 1.12 seconds
Started May 23 12:43:07 PM PDT 24
Finished May 23 12:43:12 PM PDT 24
Peak memory 196064 kb
Host smart-d50adf4f-9bca-4fe0-a391-bffc5b6d542e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016072406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.2016072406
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.2870541747
Short name T630
Test name
Test status
Simulation time 314376209 ps
CPU time 3.52 seconds
Started May 23 12:43:03 PM PDT 24
Finished May 23 12:43:08 PM PDT 24
Peak memory 197908 kb
Host smart-d9143183-da82-4afb-b3e5-5f5f59c3533b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870541747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.2870541747
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.269386723
Short name T261
Test name
Test status
Simulation time 411926846 ps
CPU time 1.9 seconds
Started May 23 12:43:06 PM PDT 24
Finished May 23 12:43:12 PM PDT 24
Peak memory 195668 kb
Host smart-bec3717b-7603-4ef1-bcd0-62cd0fa34d0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269386723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger.
269386723
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.1602788411
Short name T618
Test name
Test status
Simulation time 393923762 ps
CPU time 0.96 seconds
Started May 23 12:43:00 PM PDT 24
Finished May 23 12:43:02 PM PDT 24
Peak memory 195824 kb
Host smart-a10c1981-4ee1-4e90-84f4-4f676f7d2517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602788411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.1602788411
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.3246316458
Short name T469
Test name
Test status
Simulation time 34823947 ps
CPU time 0.9 seconds
Started May 23 12:43:03 PM PDT 24
Finished May 23 12:43:06 PM PDT 24
Peak memory 196444 kb
Host smart-65760119-7132-43c2-b12d-c11a62726268
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246316458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.3246316458
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.3714980071
Short name T460
Test name
Test status
Simulation time 1425029389 ps
CPU time 2.75 seconds
Started May 23 12:43:04 PM PDT 24
Finished May 23 12:43:09 PM PDT 24
Peak memory 197892 kb
Host smart-27eba0fe-2bd6-48b0-b43f-5234a3144949
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714980071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.3714980071
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.3405380237
Short name T161
Test name
Test status
Simulation time 19843109 ps
CPU time 0.72 seconds
Started May 23 12:43:04 PM PDT 24
Finished May 23 12:43:07 PM PDT 24
Peak memory 195192 kb
Host smart-ded3c82e-066d-49d6-9519-4c76622d0bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405380237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.3405380237
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.3646055926
Short name T260
Test name
Test status
Simulation time 53810972 ps
CPU time 1.1 seconds
Started May 23 12:43:02 PM PDT 24
Finished May 23 12:43:05 PM PDT 24
Peak memory 195696 kb
Host smart-5df2f055-3571-4140-be58-7bc6ac7a7a02
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646055926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.3646055926
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.1324943755
Short name T439
Test name
Test status
Simulation time 30002618227 ps
CPU time 52.5 seconds
Started May 23 12:43:07 PM PDT 24
Finished May 23 12:44:02 PM PDT 24
Peak memory 198060 kb
Host smart-652a5a01-7cd3-4ea1-a5a2-6dc286794a6e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324943755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.1324943755
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.1655051460
Short name T609
Test name
Test status
Simulation time 131723612333 ps
CPU time 1095.99 seconds
Started May 23 12:43:06 PM PDT 24
Finished May 23 01:01:25 PM PDT 24
Peak memory 198072 kb
Host smart-c41326a8-6ab7-4db9-a93c-987bdccc79f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1655051460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.1655051460
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.3120738044
Short name T343
Test name
Test status
Simulation time 14171823 ps
CPU time 0.62 seconds
Started May 23 12:43:11 PM PDT 24
Finished May 23 12:43:14 PM PDT 24
Peak memory 193984 kb
Host smart-5be98821-9be2-43af-b539-1d247a72fb56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120738044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.3120738044
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.3043960725
Short name T537
Test name
Test status
Simulation time 270986311 ps
CPU time 0.89 seconds
Started May 23 12:43:05 PM PDT 24
Finished May 23 12:43:09 PM PDT 24
Peak memory 195576 kb
Host smart-cdc94e17-e04e-42f1-b879-1037425ee895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043960725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.3043960725
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.2837082068
Short name T314
Test name
Test status
Simulation time 1497538813 ps
CPU time 25.39 seconds
Started May 23 12:43:09 PM PDT 24
Finished May 23 12:43:38 PM PDT 24
Peak memory 196504 kb
Host smart-359e2740-23cb-4161-865d-1af991884fa2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837082068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.2837082068
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.3569404449
Short name T604
Test name
Test status
Simulation time 107189356 ps
CPU time 0.87 seconds
Started May 23 12:43:05 PM PDT 24
Finished May 23 12:43:09 PM PDT 24
Peak memory 197068 kb
Host smart-8c342a89-1989-4a62-8b8b-1c0d622d1e1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569404449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.3569404449
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.1306898876
Short name T432
Test name
Test status
Simulation time 55182343 ps
CPU time 1.1 seconds
Started May 23 12:43:04 PM PDT 24
Finished May 23 12:43:07 PM PDT 24
Peak memory 195764 kb
Host smart-43c4a072-852c-4304-a6cc-3d331b357878
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306898876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.1306898876
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.2426707066
Short name T230
Test name
Test status
Simulation time 249797951 ps
CPU time 1.59 seconds
Started May 23 12:43:07 PM PDT 24
Finished May 23 12:43:12 PM PDT 24
Peak memory 196352 kb
Host smart-3c393041-2a78-475b-912d-55739d8163f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426707066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.2426707066
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.2466368790
Short name T243
Test name
Test status
Simulation time 84696498 ps
CPU time 1.12 seconds
Started May 23 12:43:12 PM PDT 24
Finished May 23 12:43:15 PM PDT 24
Peak memory 195780 kb
Host smart-0e2f2e7a-7c8b-4222-b17a-07171436ee82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466368790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.2466368790
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.1055958050
Short name T455
Test name
Test status
Simulation time 141644200 ps
CPU time 0.85 seconds
Started May 23 12:43:05 PM PDT 24
Finished May 23 12:43:09 PM PDT 24
Peak memory 195920 kb
Host smart-38787f14-22de-4f72-9f9b-5c97f1051b29
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055958050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.1055958050
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.677837546
Short name T22
Test name
Test status
Simulation time 397716513 ps
CPU time 1.71 seconds
Started May 23 12:43:08 PM PDT 24
Finished May 23 12:43:13 PM PDT 24
Peak memory 197864 kb
Host smart-43563044-167c-4a38-a02b-039e31ba6a95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677837546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ran
dom_long_reg_writes_reg_reads.677837546
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.3992493013
Short name T644
Test name
Test status
Simulation time 269355017 ps
CPU time 1.16 seconds
Started May 23 12:43:05 PM PDT 24
Finished May 23 12:43:09 PM PDT 24
Peak memory 195700 kb
Host smart-03380c3a-252a-4aa9-b2a0-6f5a3460a5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992493013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.3992493013
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.4172171457
Short name T650
Test name
Test status
Simulation time 451784661 ps
CPU time 1.29 seconds
Started May 23 12:43:05 PM PDT 24
Finished May 23 12:43:09 PM PDT 24
Peak memory 196624 kb
Host smart-ee72193b-ccc6-49a5-bcda-e2787d662eac
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172171457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.4172171457
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.4205541101
Short name T438
Test name
Test status
Simulation time 51743777806 ps
CPU time 170.12 seconds
Started May 23 12:43:08 PM PDT 24
Finished May 23 12:46:01 PM PDT 24
Peak memory 197960 kb
Host smart-7f968679-bcc5-4cc1-90a3-3f603f447e77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205541101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.4205541101
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.3876526245
Short name T676
Test name
Test status
Simulation time 49585540141 ps
CPU time 682.87 seconds
Started May 23 12:43:07 PM PDT 24
Finished May 23 12:54:34 PM PDT 24
Peak memory 198076 kb
Host smart-1ef29acb-3b48-4a3a-872f-0bf37808afa5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3876526245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.3876526245
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.3049336007
Short name T352
Test name
Test status
Simulation time 42280113 ps
CPU time 0.56 seconds
Started May 23 12:43:04 PM PDT 24
Finished May 23 12:43:07 PM PDT 24
Peak memory 193768 kb
Host smart-c8371ecc-113c-464d-ae2e-7d149f7f07b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049336007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.3049336007
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.1969018299
Short name T659
Test name
Test status
Simulation time 40717250 ps
CPU time 0.84 seconds
Started May 23 12:43:06 PM PDT 24
Finished May 23 12:43:10 PM PDT 24
Peak memory 197140 kb
Host smart-38796511-8f63-40f4-9199-0a54a7096169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969018299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.1969018299
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.1072387831
Short name T290
Test name
Test status
Simulation time 397928368 ps
CPU time 14.22 seconds
Started May 23 12:43:07 PM PDT 24
Finished May 23 12:43:25 PM PDT 24
Peak memory 197836 kb
Host smart-cd167104-8a28-4470-b0eb-8df55f5e269b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072387831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.1072387831
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.2503334276
Short name T239
Test name
Test status
Simulation time 327406845 ps
CPU time 1.09 seconds
Started May 23 12:43:09 PM PDT 24
Finished May 23 12:43:13 PM PDT 24
Peak memory 196836 kb
Host smart-3c885d62-2240-403a-b175-c9817336a132
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503334276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.2503334276
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.3503894114
Short name T479
Test name
Test status
Simulation time 34588158 ps
CPU time 0.8 seconds
Started May 23 12:43:05 PM PDT 24
Finished May 23 12:43:08 PM PDT 24
Peak memory 196208 kb
Host smart-411f0aa6-96b2-4a90-94ca-b203af3525c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503894114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.3503894114
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.4192160582
Short name T75
Test name
Test status
Simulation time 112380537 ps
CPU time 2.16 seconds
Started May 23 12:43:09 PM PDT 24
Finished May 23 12:43:14 PM PDT 24
Peak memory 195984 kb
Host smart-6459ec65-e5b4-433c-a8c5-87445e13eba1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192160582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.4192160582
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.4239369713
Short name T114
Test name
Test status
Simulation time 121680441 ps
CPU time 1.13 seconds
Started May 23 12:43:09 PM PDT 24
Finished May 23 12:43:13 PM PDT 24
Peak memory 195360 kb
Host smart-f21124f5-bf09-4f9f-b427-c89b2490279e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239369713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.4239369713
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.2003514374
Short name T431
Test name
Test status
Simulation time 14426248 ps
CPU time 0.71 seconds
Started May 23 12:43:11 PM PDT 24
Finished May 23 12:43:14 PM PDT 24
Peak memory 195308 kb
Host smart-48b41e69-4358-4825-b20e-6b0249c957b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003514374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.2003514374
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.3506819471
Short name T565
Test name
Test status
Simulation time 45073118 ps
CPU time 1.09 seconds
Started May 23 12:43:13 PM PDT 24
Finished May 23 12:43:21 PM PDT 24
Peak memory 196528 kb
Host smart-cabc73b3-ce52-46e0-9d7d-f7624eb4ec3c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506819471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.3506819471
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.915591606
Short name T204
Test name
Test status
Simulation time 42906191 ps
CPU time 1.91 seconds
Started May 23 12:43:05 PM PDT 24
Finished May 23 12:43:10 PM PDT 24
Peak memory 197916 kb
Host smart-64d54a8b-121d-4597-bf82-2d870fa9d6c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915591606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ran
dom_long_reg_writes_reg_reads.915591606
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.82245581
Short name T167
Test name
Test status
Simulation time 47118594 ps
CPU time 1.19 seconds
Started May 23 12:43:05 PM PDT 24
Finished May 23 12:43:09 PM PDT 24
Peak memory 195720 kb
Host smart-d717ee2a-7d78-4e75-91b8-6b563bff1865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82245581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.82245581
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.2433634531
Short name T564
Test name
Test status
Simulation time 410890026 ps
CPU time 1.04 seconds
Started May 23 12:43:06 PM PDT 24
Finished May 23 12:43:10 PM PDT 24
Peak memory 195440 kb
Host smart-4a246e8d-7cc2-4e4f-a540-eace48de97d4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433634531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.2433634531
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.2838100184
Short name T210
Test name
Test status
Simulation time 7769535658 ps
CPU time 194.98 seconds
Started May 23 12:43:05 PM PDT 24
Finished May 23 12:46:22 PM PDT 24
Peak memory 197992 kb
Host smart-586a7675-b061-491c-a1cf-83b63ce49db0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838100184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.2838100184
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.1334749283
Short name T66
Test name
Test status
Simulation time 79573000333 ps
CPU time 1876.23 seconds
Started May 23 12:43:05 PM PDT 24
Finished May 23 01:14:25 PM PDT 24
Peak memory 198156 kb
Host smart-1aba7fc5-d711-424c-bde5-393e3e1de0bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1334749283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.1334749283
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.3820241819
Short name T621
Test name
Test status
Simulation time 14903161 ps
CPU time 0.6 seconds
Started May 23 12:43:15 PM PDT 24
Finished May 23 12:43:16 PM PDT 24
Peak memory 193872 kb
Host smart-780777d7-b048-4275-90b4-91253bb7f415
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820241819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.3820241819
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.4199023707
Short name T207
Test name
Test status
Simulation time 155339254 ps
CPU time 0.9 seconds
Started May 23 12:43:12 PM PDT 24
Finished May 23 12:43:15 PM PDT 24
Peak memory 196276 kb
Host smart-29b07641-1615-4a4f-8cef-f7b5fd7a578f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199023707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.4199023707
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.3515351809
Short name T223
Test name
Test status
Simulation time 1681770822 ps
CPU time 21.95 seconds
Started May 23 12:43:22 PM PDT 24
Finished May 23 12:43:48 PM PDT 24
Peak memory 196304 kb
Host smart-e64eab86-35f3-456c-bc29-3753d5881e19
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515351809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.3515351809
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.2502667454
Short name T444
Test name
Test status
Simulation time 30183699 ps
CPU time 0.62 seconds
Started May 23 12:43:16 PM PDT 24
Finished May 23 12:43:18 PM PDT 24
Peak memory 194384 kb
Host smart-e07e8483-a184-4797-9916-bce7db70792f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502667454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.2502667454
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.2140685618
Short name T478
Test name
Test status
Simulation time 172380731 ps
CPU time 1.01 seconds
Started May 23 12:43:04 PM PDT 24
Finished May 23 12:43:07 PM PDT 24
Peak memory 195904 kb
Host smart-6efa3f25-68e2-4acc-a30f-53bbdfe1386a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140685618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.2140685618
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.1855237195
Short name T577
Test name
Test status
Simulation time 126297894 ps
CPU time 1.53 seconds
Started May 23 12:43:15 PM PDT 24
Finished May 23 12:43:19 PM PDT 24
Peak memory 196512 kb
Host smart-a5450a96-355a-4c99-9d8c-7242a33b76f0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855237195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.1855237195
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.1085045007
Short name T24
Test name
Test status
Simulation time 506621947 ps
CPU time 2.55 seconds
Started May 23 12:43:16 PM PDT 24
Finished May 23 12:43:22 PM PDT 24
Peak memory 196376 kb
Host smart-9b6c5ee4-4407-43c4-9a08-3d57596c43ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085045007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.1085045007
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.1535588652
Short name T489
Test name
Test status
Simulation time 21358934 ps
CPU time 0.85 seconds
Started May 23 12:43:06 PM PDT 24
Finished May 23 12:43:10 PM PDT 24
Peak memory 195976 kb
Host smart-aa3c7598-0b9a-4c48-a5ce-062da738456c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535588652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.1535588652
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.3945289775
Short name T344
Test name
Test status
Simulation time 18700729 ps
CPU time 0.66 seconds
Started May 23 12:43:11 PM PDT 24
Finished May 23 12:43:14 PM PDT 24
Peak memory 194176 kb
Host smart-c3e2f9f8-fb36-4a82-ba1c-50233d08e3b1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945289775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.3945289775
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.3209723130
Short name T440
Test name
Test status
Simulation time 1480926590 ps
CPU time 5.15 seconds
Started May 23 12:43:16 PM PDT 24
Finished May 23 12:43:23 PM PDT 24
Peak memory 197864 kb
Host smart-a8cbab16-f6fb-4326-b807-d86ec6cd8c7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209723130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.3209723130
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.379687647
Short name T500
Test name
Test status
Simulation time 41521338 ps
CPU time 1.1 seconds
Started May 23 12:43:05 PM PDT 24
Finished May 23 12:43:09 PM PDT 24
Peak memory 195380 kb
Host smart-9c5b32b0-24e1-4c84-acb1-339c55a7606b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379687647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.379687647
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.260061089
Short name T556
Test name
Test status
Simulation time 136950805 ps
CPU time 0.83 seconds
Started May 23 12:43:06 PM PDT 24
Finished May 23 12:43:11 PM PDT 24
Peak memory 195196 kb
Host smart-cc4096dc-db8f-4bfa-9661-556ee1db17e0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260061089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.260061089
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.1723689278
Short name T464
Test name
Test status
Simulation time 44752409258 ps
CPU time 67.06 seconds
Started May 23 12:43:16 PM PDT 24
Finished May 23 12:44:26 PM PDT 24
Peak memory 198052 kb
Host smart-9bb00d1f-8b27-4667-bf87-86183ad1e29d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723689278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.1723689278
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.1191862942
Short name T282
Test name
Test status
Simulation time 19643915 ps
CPU time 0.57 seconds
Started May 23 12:43:14 PM PDT 24
Finished May 23 12:43:16 PM PDT 24
Peak memory 194552 kb
Host smart-a2f99850-d17b-41cd-ba32-81add9f633f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191862942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.1191862942
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.427165820
Short name T127
Test name
Test status
Simulation time 51187464 ps
CPU time 0.72 seconds
Started May 23 12:43:16 PM PDT 24
Finished May 23 12:43:19 PM PDT 24
Peak memory 194836 kb
Host smart-5746ee0c-f114-435d-aa37-65e3339c74ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427165820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.427165820
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.3945170474
Short name T675
Test name
Test status
Simulation time 4340857553 ps
CPU time 22.96 seconds
Started May 23 12:43:18 PM PDT 24
Finished May 23 12:43:44 PM PDT 24
Peak memory 197988 kb
Host smart-d79dcbf3-2ac9-44bc-88dc-8ec77c0d37c3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945170474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.3945170474
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.1062391667
Short name T33
Test name
Test status
Simulation time 620540182 ps
CPU time 0.88 seconds
Started May 23 12:43:16 PM PDT 24
Finished May 23 12:43:18 PM PDT 24
Peak memory 195816 kb
Host smart-34197dd2-d197-4760-90b2-fd6118adc975
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062391667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.1062391667
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.3473528252
Short name T193
Test name
Test status
Simulation time 73572094 ps
CPU time 1.21 seconds
Started May 23 12:43:16 PM PDT 24
Finished May 23 12:43:19 PM PDT 24
Peak memory 196696 kb
Host smart-9cf487e5-e612-4397-99e2-e402cf1c1cad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473528252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.3473528252
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.4141437284
Short name T416
Test name
Test status
Simulation time 517771108 ps
CPU time 3.12 seconds
Started May 23 12:43:16 PM PDT 24
Finished May 23 12:43:21 PM PDT 24
Peak memory 197788 kb
Host smart-bd343cae-9e7f-40bc-8782-9d91afbb1c9a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141437284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.4141437284
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.4148659931
Short name T689
Test name
Test status
Simulation time 171066635 ps
CPU time 3.28 seconds
Started May 23 12:43:16 PM PDT 24
Finished May 23 12:43:21 PM PDT 24
Peak memory 196848 kb
Host smart-cec373df-98db-4769-8fa3-71478c73bc39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148659931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.4148659931
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.869799402
Short name T401
Test name
Test status
Simulation time 25200767 ps
CPU time 0.97 seconds
Started May 23 12:43:17 PM PDT 24
Finished May 23 12:43:22 PM PDT 24
Peak memory 196544 kb
Host smart-8817f805-7865-45f8-8b05-418abe389b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869799402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.869799402
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.4081518590
Short name T504
Test name
Test status
Simulation time 42239954 ps
CPU time 0.99 seconds
Started May 23 12:43:16 PM PDT 24
Finished May 23 12:43:20 PM PDT 24
Peak memory 195704 kb
Host smart-c0db3d4c-248d-4621-9cf5-21aead0a0775
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081518590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.4081518590
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.4078083906
Short name T11
Test name
Test status
Simulation time 569722951 ps
CPU time 4.66 seconds
Started May 23 12:43:16 PM PDT 24
Finished May 23 12:43:23 PM PDT 24
Peak memory 197864 kb
Host smart-84cff879-9463-45ec-b13d-7fa2231a7ddf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078083906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.4078083906
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.2564387090
Short name T681
Test name
Test status
Simulation time 159479266 ps
CPU time 1 seconds
Started May 23 12:43:16 PM PDT 24
Finished May 23 12:43:20 PM PDT 24
Peak memory 196432 kb
Host smart-332073d4-8c28-4d2b-909f-d2abf1eb8da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564387090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.2564387090
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.1506434355
Short name T680
Test name
Test status
Simulation time 28869553 ps
CPU time 0.88 seconds
Started May 23 12:43:15 PM PDT 24
Finished May 23 12:43:18 PM PDT 24
Peak memory 197196 kb
Host smart-ca373a18-09f7-491d-8680-99a1a7f9ae89
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506434355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.1506434355
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.2007567720
Short name T283
Test name
Test status
Simulation time 21638815452 ps
CPU time 147.31 seconds
Started May 23 12:43:17 PM PDT 24
Finished May 23 12:45:47 PM PDT 24
Peak memory 198048 kb
Host smart-0ae66fc0-e66f-4cb1-a37d-7467bdb35db5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007567720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.2007567720
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.1612547275
Short name T398
Test name
Test status
Simulation time 33195814 ps
CPU time 0.57 seconds
Started May 23 12:43:15 PM PDT 24
Finished May 23 12:43:17 PM PDT 24
Peak memory 194428 kb
Host smart-af47aa69-c8e0-465c-8650-e1889fdf5228
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612547275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.1612547275
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.2980163898
Short name T294
Test name
Test status
Simulation time 35019361 ps
CPU time 0.71 seconds
Started May 23 12:43:17 PM PDT 24
Finished May 23 12:43:21 PM PDT 24
Peak memory 193764 kb
Host smart-2c3eab7f-4b9f-4e81-aef2-208f36fd7967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980163898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.2980163898
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.3282530405
Short name T146
Test name
Test status
Simulation time 423677032 ps
CPU time 11.72 seconds
Started May 23 12:43:16 PM PDT 24
Finished May 23 12:43:30 PM PDT 24
Peak memory 196760 kb
Host smart-5eb352f3-eea2-4d30-a666-86ecc9c9cfcd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282530405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.3282530405
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.504379959
Short name T513
Test name
Test status
Simulation time 106125526 ps
CPU time 0.7 seconds
Started May 23 12:43:23 PM PDT 24
Finished May 23 12:43:27 PM PDT 24
Peak memory 195352 kb
Host smart-0063a033-e5ae-4ef9-a376-21658c1a3071
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504379959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.504379959
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.409280491
Short name T461
Test name
Test status
Simulation time 358535779 ps
CPU time 1.36 seconds
Started May 23 12:43:17 PM PDT 24
Finished May 23 12:43:22 PM PDT 24
Peak memory 196956 kb
Host smart-ac809492-1c8f-4dc9-8e95-bd1fab120230
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409280491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.409280491
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.2916455279
Short name T148
Test name
Test status
Simulation time 144013666 ps
CPU time 1.92 seconds
Started May 23 12:43:15 PM PDT 24
Finished May 23 12:43:17 PM PDT 24
Peak memory 197900 kb
Host smart-6cd96b6e-ed3f-45ab-9240-24ea6200adad
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916455279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.2916455279
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.2814647375
Short name T634
Test name
Test status
Simulation time 91784981 ps
CPU time 2.17 seconds
Started May 23 12:43:19 PM PDT 24
Finished May 23 12:43:25 PM PDT 24
Peak memory 197096 kb
Host smart-cc18c00c-3272-4a50-a474-1bac20decd41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814647375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.2814647375
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.3278406517
Short name T59
Test name
Test status
Simulation time 121513716 ps
CPU time 1.3 seconds
Started May 23 12:43:16 PM PDT 24
Finished May 23 12:43:19 PM PDT 24
Peak memory 197792 kb
Host smart-b06eff17-a8a2-49a3-80b9-787baf86049b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278406517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.3278406517
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.1486687444
Short name T229
Test name
Test status
Simulation time 30987248 ps
CPU time 1.13 seconds
Started May 23 12:43:17 PM PDT 24
Finished May 23 12:43:21 PM PDT 24
Peak memory 196464 kb
Host smart-09f68883-9594-4031-a5c7-e597bc8c14e3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486687444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.1486687444
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.3829339426
Short name T583
Test name
Test status
Simulation time 199550755 ps
CPU time 4.37 seconds
Started May 23 12:43:15 PM PDT 24
Finished May 23 12:43:21 PM PDT 24
Peak memory 197956 kb
Host smart-8c6b780e-623d-49b1-9a4a-b6990ffc523d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829339426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.3829339426
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.3761917791
Short name T115
Test name
Test status
Simulation time 81472323 ps
CPU time 0.8 seconds
Started May 23 12:43:16 PM PDT 24
Finished May 23 12:43:18 PM PDT 24
Peak memory 195192 kb
Host smart-69678c6d-3af3-45bb-b59e-2b31541c3b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761917791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.3761917791
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.2511755726
Short name T338
Test name
Test status
Simulation time 38831332 ps
CPU time 1.14 seconds
Started May 23 12:43:17 PM PDT 24
Finished May 23 12:43:21 PM PDT 24
Peak memory 196352 kb
Host smart-e49df928-2da5-4dbc-8e14-e9a56833d64e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511755726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.2511755726
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.3216571808
Short name T707
Test name
Test status
Simulation time 22543725498 ps
CPU time 154.68 seconds
Started May 23 12:43:16 PM PDT 24
Finished May 23 12:45:53 PM PDT 24
Peak memory 198196 kb
Host smart-f6cd33c6-b478-4069-b31b-80faba4b67d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216571808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.3216571808
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.415057766
Short name T71
Test name
Test status
Simulation time 78185985190 ps
CPU time 900.11 seconds
Started May 23 12:43:20 PM PDT 24
Finished May 23 12:58:23 PM PDT 24
Peak memory 198120 kb
Host smart-3c2564cb-c5f5-4f51-82ea-b22493f16e46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=415057766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.415057766
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.3521142915
Short name T486
Test name
Test status
Simulation time 12377730 ps
CPU time 0.56 seconds
Started May 23 12:43:17 PM PDT 24
Finished May 23 12:43:21 PM PDT 24
Peak memory 194572 kb
Host smart-9c270bda-3dd8-4576-b89c-6cbf3579f6c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521142915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.3521142915
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.820073538
Short name T178
Test name
Test status
Simulation time 72948608 ps
CPU time 0.79 seconds
Started May 23 12:43:16 PM PDT 24
Finished May 23 12:43:20 PM PDT 24
Peak memory 195260 kb
Host smart-1c2cf8e5-2142-4145-b4c1-d10c8ffd0d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820073538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.820073538
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.407656336
Short name T393
Test name
Test status
Simulation time 1839017385 ps
CPU time 14.39 seconds
Started May 23 12:43:24 PM PDT 24
Finished May 23 12:43:41 PM PDT 24
Peak memory 195408 kb
Host smart-acd9295b-5b32-4138-8ede-224740ca7fab
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407656336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stres
s.407656336
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.2729076875
Short name T328
Test name
Test status
Simulation time 91364449 ps
CPU time 1.12 seconds
Started May 23 12:43:19 PM PDT 24
Finished May 23 12:43:24 PM PDT 24
Peak memory 196504 kb
Host smart-f093a052-9a20-44d3-a6f7-44afbfac4ed7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729076875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.2729076875
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.1767955142
Short name T446
Test name
Test status
Simulation time 114905908 ps
CPU time 0.71 seconds
Started May 23 12:43:24 PM PDT 24
Finished May 23 12:43:28 PM PDT 24
Peak memory 195424 kb
Host smart-1bf3404d-6b2a-443e-8e03-2046b29be92c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767955142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.1767955142
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.3629962777
Short name T273
Test name
Test status
Simulation time 271857167 ps
CPU time 3.06 seconds
Started May 23 12:43:17 PM PDT 24
Finished May 23 12:43:24 PM PDT 24
Peak memory 198000 kb
Host smart-d97cf005-94fc-4064-b941-d943273d177a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629962777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.3629962777
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.3698971023
Short name T459
Test name
Test status
Simulation time 121006360 ps
CPU time 3.46 seconds
Started May 23 12:43:18 PM PDT 24
Finished May 23 12:43:25 PM PDT 24
Peak memory 197016 kb
Host smart-63f39708-e5b0-432f-9129-1ed036467f78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698971023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.3698971023
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.2019264936
Short name T435
Test name
Test status
Simulation time 45057922 ps
CPU time 1.04 seconds
Started May 23 12:43:25 PM PDT 24
Finished May 23 12:43:29 PM PDT 24
Peak memory 195960 kb
Host smart-f49b9b92-0de2-40fe-beb7-a97f6821783f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019264936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.2019264936
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.1952585374
Short name T303
Test name
Test status
Simulation time 119052931 ps
CPU time 1.38 seconds
Started May 23 12:43:22 PM PDT 24
Finished May 23 12:43:27 PM PDT 24
Peak memory 196996 kb
Host smart-c607b7ac-fb4c-4ee8-81a0-95e1abb9fcdb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952585374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.1952585374
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.3395235442
Short name T638
Test name
Test status
Simulation time 683626933 ps
CPU time 4.38 seconds
Started May 23 12:43:16 PM PDT 24
Finished May 23 12:43:24 PM PDT 24
Peak memory 197852 kb
Host smart-1948d301-7589-41dc-bfbd-fee1bf45958a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395235442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.3395235442
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.283347576
Short name T208
Test name
Test status
Simulation time 85091668 ps
CPU time 0.97 seconds
Started May 23 12:43:18 PM PDT 24
Finished May 23 12:43:23 PM PDT 24
Peak memory 195608 kb
Host smart-1a9c367d-1543-4aac-89e2-e670873597f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283347576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.283347576
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.34712535
Short name T568
Test name
Test status
Simulation time 63911685 ps
CPU time 1.25 seconds
Started May 23 12:43:23 PM PDT 24
Finished May 23 12:43:28 PM PDT 24
Peak memory 195672 kb
Host smart-9615a44e-216a-428e-a56a-c8be55cb1ba4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34712535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.34712535
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.1189160252
Short name T445
Test name
Test status
Simulation time 13738127146 ps
CPU time 181.68 seconds
Started May 23 12:43:16 PM PDT 24
Finished May 23 12:46:21 PM PDT 24
Peak memory 197344 kb
Host smart-9b217240-3223-4ea6-9fcb-b84ec4149612
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189160252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.1189160252
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.1091893176
Short name T509
Test name
Test status
Simulation time 40916175 ps
CPU time 0.58 seconds
Started May 23 12:43:24 PM PDT 24
Finished May 23 12:43:28 PM PDT 24
Peak memory 194040 kb
Host smart-1774a3bc-4871-414d-90cb-581207742e8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091893176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.1091893176
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.4137817735
Short name T206
Test name
Test status
Simulation time 17861046 ps
CPU time 0.64 seconds
Started May 23 12:43:19 PM PDT 24
Finished May 23 12:43:23 PM PDT 24
Peak memory 194012 kb
Host smart-51aa71aa-9c74-411c-8f3d-2ac8679604b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137817735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.4137817735
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.2865631893
Short name T182
Test name
Test status
Simulation time 487642692 ps
CPU time 17.1 seconds
Started May 23 12:43:18 PM PDT 24
Finished May 23 12:43:39 PM PDT 24
Peak memory 196664 kb
Host smart-f1b5cc9a-cb6d-4304-9697-58a25d1714ba
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865631893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.2865631893
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.1371732157
Short name T331
Test name
Test status
Simulation time 158241991 ps
CPU time 0.74 seconds
Started May 23 12:43:19 PM PDT 24
Finished May 23 12:43:23 PM PDT 24
Peak memory 195656 kb
Host smart-533a6710-a252-4377-9c26-3cb580d8a73a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371732157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.1371732157
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.4035607000
Short name T642
Test name
Test status
Simulation time 74322158 ps
CPU time 1.26 seconds
Started May 23 12:43:18 PM PDT 24
Finished May 23 12:43:23 PM PDT 24
Peak memory 196904 kb
Host smart-21dd90e9-98b0-41cd-a13a-e95465477b50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035607000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.4035607000
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.1569128981
Short name T596
Test name
Test status
Simulation time 80639083 ps
CPU time 3.05 seconds
Started May 23 12:43:18 PM PDT 24
Finished May 23 12:43:25 PM PDT 24
Peak memory 197952 kb
Host smart-3ee47061-e81f-4334-a11c-d97319f9692f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569128981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.1569128981
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.341763505
Short name T417
Test name
Test status
Simulation time 523166590 ps
CPU time 3.19 seconds
Started May 23 12:43:15 PM PDT 24
Finished May 23 12:43:21 PM PDT 24
Peak memory 197028 kb
Host smart-ca9d2f0d-997c-4be5-a8ae-658480f13ace
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341763505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger.
341763505
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.3863026200
Short name T361
Test name
Test status
Simulation time 153659399 ps
CPU time 1.27 seconds
Started May 23 12:43:16 PM PDT 24
Finished May 23 12:43:21 PM PDT 24
Peak memory 195776 kb
Host smart-90107b61-eb5d-4e1f-94ef-d4275931c9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863026200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.3863026200
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.1321861807
Short name T382
Test name
Test status
Simulation time 107051761 ps
CPU time 1.04 seconds
Started May 23 12:43:15 PM PDT 24
Finished May 23 12:43:18 PM PDT 24
Peak memory 195712 kb
Host smart-6e1fed42-48b6-4377-ab82-57072e5a70f2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321861807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.1321861807
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.2393872647
Short name T6
Test name
Test status
Simulation time 1343147984 ps
CPU time 3.71 seconds
Started May 23 12:43:21 PM PDT 24
Finished May 23 12:43:27 PM PDT 24
Peak memory 197356 kb
Host smart-f490f0b8-83c9-434e-b290-c3bbd58958ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393872647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.2393872647
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.1838582434
Short name T651
Test name
Test status
Simulation time 67262161 ps
CPU time 1.11 seconds
Started May 23 12:43:18 PM PDT 24
Finished May 23 12:43:23 PM PDT 24
Peak memory 195520 kb
Host smart-39f193a5-a3d2-460b-bc26-b1969c825468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838582434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.1838582434
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.767263032
Short name T221
Test name
Test status
Simulation time 37603038 ps
CPU time 1.03 seconds
Started May 23 12:43:17 PM PDT 24
Finished May 23 12:43:22 PM PDT 24
Peak memory 195628 kb
Host smart-1f511928-fbd2-4d88-b7a1-da4a8b0dbb03
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767263032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.767263032
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.1969646364
Short name T144
Test name
Test status
Simulation time 4602615142 ps
CPU time 97.32 seconds
Started May 23 12:43:24 PM PDT 24
Finished May 23 12:45:04 PM PDT 24
Peak memory 198140 kb
Host smart-03b0dd0c-33de-428b-a01a-7818d235ac71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969646364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.1969646364
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.1319162113
Short name T605
Test name
Test status
Simulation time 59094484716 ps
CPU time 1078.76 seconds
Started May 23 12:43:21 PM PDT 24
Finished May 23 01:01:23 PM PDT 24
Peak memory 198188 kb
Host smart-5f477c52-9478-49ff-981a-c3b64f04601d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1319162113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.1319162113
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.3808078289
Short name T339
Test name
Test status
Simulation time 43401548 ps
CPU time 0.57 seconds
Started May 23 12:43:20 PM PDT 24
Finished May 23 12:43:24 PM PDT 24
Peak memory 194492 kb
Host smart-3febed88-b508-4d39-9204-df7cb51ed9f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808078289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.3808078289
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.2592268044
Short name T562
Test name
Test status
Simulation time 92293327 ps
CPU time 0.7 seconds
Started May 23 12:43:21 PM PDT 24
Finished May 23 12:43:24 PM PDT 24
Peak memory 194144 kb
Host smart-97e8c86d-86a5-4d67-97ea-1792ac96e0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592268044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.2592268044
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.2835267426
Short name T591
Test name
Test status
Simulation time 1316178483 ps
CPU time 11.22 seconds
Started May 23 12:43:17 PM PDT 24
Finished May 23 12:43:32 PM PDT 24
Peak memory 196536 kb
Host smart-64aa160d-961d-465a-99fa-0cfde66f08ab
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835267426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.2835267426
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.1839361395
Short name T72
Test name
Test status
Simulation time 158929414 ps
CPU time 0.8 seconds
Started May 23 12:43:18 PM PDT 24
Finished May 23 12:43:22 PM PDT 24
Peak memory 195828 kb
Host smart-48f64e07-e75b-44ba-9ba0-db9ba6ac06d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839361395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.1839361395
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.1569809731
Short name T29
Test name
Test status
Simulation time 321205202 ps
CPU time 1.16 seconds
Started May 23 12:43:17 PM PDT 24
Finished May 23 12:43:22 PM PDT 24
Peak memory 195684 kb
Host smart-38095a35-baaa-4c0a-95b8-0020ae5b19e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569809731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.1569809731
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.414625481
Short name T538
Test name
Test status
Simulation time 300107142 ps
CPU time 3.04 seconds
Started May 23 12:43:22 PM PDT 24
Finished May 23 12:43:28 PM PDT 24
Peak memory 197852 kb
Host smart-746215d5-71b3-4228-af79-44af473e0b83
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414625481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.gpio_intr_with_filter_rand_intr_event.414625481
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.1554170819
Short name T530
Test name
Test status
Simulation time 880378571 ps
CPU time 2.69 seconds
Started May 23 12:43:21 PM PDT 24
Finished May 23 12:43:27 PM PDT 24
Peak memory 197860 kb
Host smart-126b2b93-4460-4cac-ad68-c42cf777b88f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554170819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.1554170819
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.217168658
Short name T113
Test name
Test status
Simulation time 15155692 ps
CPU time 0.72 seconds
Started May 23 12:43:26 PM PDT 24
Finished May 23 12:43:29 PM PDT 24
Peak memory 195296 kb
Host smart-0e2398f1-26d1-4266-a717-3b791b17db9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217168658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.217168658
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.2362846565
Short name T473
Test name
Test status
Simulation time 64287705 ps
CPU time 0.86 seconds
Started May 23 12:43:21 PM PDT 24
Finished May 23 12:43:25 PM PDT 24
Peak memory 196280 kb
Host smart-72c128b8-a22c-46fe-b108-21899c1283c4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362846565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.2362846565
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.522935379
Short name T404
Test name
Test status
Simulation time 263580357 ps
CPU time 5.23 seconds
Started May 23 12:43:21 PM PDT 24
Finished May 23 12:43:29 PM PDT 24
Peak memory 197760 kb
Host smart-03896dd6-75bb-4c7f-b96c-8d4fc7110591
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522935379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ran
dom_long_reg_writes_reg_reads.522935379
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.631717517
Short name T176
Test name
Test status
Simulation time 57348986 ps
CPU time 1.1 seconds
Started May 23 12:43:20 PM PDT 24
Finished May 23 12:43:24 PM PDT 24
Peak memory 196472 kb
Host smart-8336e29e-8389-4220-9847-ff711b19ae30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631717517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.631717517
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.1625688754
Short name T279
Test name
Test status
Simulation time 76623283 ps
CPU time 1.35 seconds
Started May 23 12:43:20 PM PDT 24
Finished May 23 12:43:24 PM PDT 24
Peak memory 196808 kb
Host smart-7185c22e-730a-40ed-bbbe-ad0feb3989bb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625688754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.1625688754
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.1480702926
Short name T9
Test name
Test status
Simulation time 11905711686 ps
CPU time 133.94 seconds
Started May 23 12:43:19 PM PDT 24
Finished May 23 12:45:36 PM PDT 24
Peak memory 198140 kb
Host smart-883dacff-243a-4ff6-8f34-712281e96ccc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480702926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.1480702926
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.910024432
Short name T505
Test name
Test status
Simulation time 156447507 ps
CPU time 0.9 seconds
Started May 23 12:41:52 PM PDT 24
Finished May 23 12:41:56 PM PDT 24
Peak memory 196476 kb
Host smart-c7bb4489-da86-4114-8679-e2ac39f13395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910024432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.910024432
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.3594335788
Short name T142
Test name
Test status
Simulation time 473765991 ps
CPU time 4.5 seconds
Started May 23 12:41:52 PM PDT 24
Finished May 23 12:41:59 PM PDT 24
Peak memory 196576 kb
Host smart-23e825e2-d208-4ff0-b863-be639afff50e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594335788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.3594335788
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.2363123565
Short name T405
Test name
Test status
Simulation time 216834701 ps
CPU time 0.9 seconds
Started May 23 12:41:53 PM PDT 24
Finished May 23 12:41:56 PM PDT 24
Peak memory 195788 kb
Host smart-c00f9868-58d7-49ef-b7f8-3a154b066655
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363123565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.2363123565
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.4253355867
Short name T268
Test name
Test status
Simulation time 109362157 ps
CPU time 1.54 seconds
Started May 23 12:41:52 PM PDT 24
Finished May 23 12:41:57 PM PDT 24
Peak memory 196892 kb
Host smart-377095d1-2b94-4d52-af1c-380f51677560
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253355867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.4253355867
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.3692140133
Short name T623
Test name
Test status
Simulation time 342519880 ps
CPU time 3.69 seconds
Started May 23 12:41:52 PM PDT 24
Finished May 23 12:41:59 PM PDT 24
Peak memory 198068 kb
Host smart-108b83d7-91b5-460b-aa2d-1e6ff194396c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692140133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.3692140133
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.2246983354
Short name T413
Test name
Test status
Simulation time 88552391 ps
CPU time 2.01 seconds
Started May 23 12:41:52 PM PDT 24
Finished May 23 12:41:57 PM PDT 24
Peak memory 196040 kb
Host smart-d7d16e6d-d6f7-4700-83b0-65d49115bc84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246983354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
2246983354
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.1025506324
Short name T278
Test name
Test status
Simulation time 15191168 ps
CPU time 0.72 seconds
Started May 23 12:41:50 PM PDT 24
Finished May 23 12:41:53 PM PDT 24
Peak memory 196008 kb
Host smart-c7772dbd-d6c2-4ac3-b803-62c3f66a3def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025506324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.1025506324
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.1290550814
Short name T580
Test name
Test status
Simulation time 80370540 ps
CPU time 0.89 seconds
Started May 23 12:41:50 PM PDT 24
Finished May 23 12:41:54 PM PDT 24
Peak memory 195748 kb
Host smart-dbe47eaf-9081-4ee3-876b-16a8884081d1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290550814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.1290550814
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.1386025277
Short name T532
Test name
Test status
Simulation time 401745085 ps
CPU time 4.13 seconds
Started May 23 12:41:52 PM PDT 24
Finished May 23 12:41:59 PM PDT 24
Peak memory 197668 kb
Host smart-1770638d-529a-4332-a7d5-853282ea4bfd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386025277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.1386025277
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.4274503153
Short name T57
Test name
Test status
Simulation time 145393615 ps
CPU time 0.83 seconds
Started May 23 12:42:02 PM PDT 24
Finished May 23 12:42:04 PM PDT 24
Peak memory 213504 kb
Host smart-3735b666-ef20-4935-8002-b5a19945acd6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274503153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.4274503153
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.3706124199
Short name T26
Test name
Test status
Simulation time 280889241 ps
CPU time 1.32 seconds
Started May 23 12:41:52 PM PDT 24
Finished May 23 12:41:56 PM PDT 24
Peak memory 195656 kb
Host smart-b477a6ea-dccc-4503-9f22-9e3614d49a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706124199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.3706124199
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.4021578187
Short name T214
Test name
Test status
Simulation time 139247306 ps
CPU time 0.89 seconds
Started May 23 12:41:52 PM PDT 24
Finished May 23 12:41:56 PM PDT 24
Peak memory 195148 kb
Host smart-4901226e-83b5-4256-ab36-7777f24b4d91
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021578187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.4021578187
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.538891972
Short name T81
Test name
Test status
Simulation time 2308614145 ps
CPU time 32.16 seconds
Started May 23 12:41:52 PM PDT 24
Finished May 23 12:42:27 PM PDT 24
Peak memory 197944 kb
Host smart-76cf1f11-fbe9-4937-8d1c-7b7fce0c1210
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538891972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gp
io_stress_all.538891972
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.31376708
Short name T36
Test name
Test status
Simulation time 219631236398 ps
CPU time 739.91 seconds
Started May 23 12:42:04 PM PDT 24
Finished May 23 12:54:26 PM PDT 24
Peak memory 198172 kb
Host smart-dfd01adc-cd88-4384-8800-cdbc17f638d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=31376708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.31376708
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.3685654407
Short name T558
Test name
Test status
Simulation time 40223270 ps
CPU time 0.63 seconds
Started May 23 12:43:19 PM PDT 24
Finished May 23 12:43:23 PM PDT 24
Peak memory 194696 kb
Host smart-5f7b6b48-d5a1-49c4-8980-2d640b281ce4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685654407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.3685654407
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.3655854349
Short name T553
Test name
Test status
Simulation time 37655470 ps
CPU time 0.83 seconds
Started May 23 12:43:17 PM PDT 24
Finished May 23 12:43:21 PM PDT 24
Peak memory 195252 kb
Host smart-d5808ce2-998f-4d61-a9e5-630f8d5dca45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655854349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.3655854349
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.419132153
Short name T408
Test name
Test status
Simulation time 513111788 ps
CPU time 5.98 seconds
Started May 23 12:43:30 PM PDT 24
Finished May 23 12:43:39 PM PDT 24
Peak memory 197884 kb
Host smart-4e56f8a6-f8b7-40d6-a47a-9e7ec400ee06
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419132153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stres
s.419132153
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.31052740
Short name T184
Test name
Test status
Simulation time 33925114 ps
CPU time 0.85 seconds
Started May 23 12:43:30 PM PDT 24
Finished May 23 12:43:34 PM PDT 24
Peak memory 196484 kb
Host smart-9c8ae699-00a2-47ea-a9c9-f8d945754c36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31052740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.31052740
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.2349293295
Short name T392
Test name
Test status
Simulation time 88348176 ps
CPU time 0.72 seconds
Started May 23 12:43:18 PM PDT 24
Finished May 23 12:43:22 PM PDT 24
Peak memory 196040 kb
Host smart-3d3bea11-920d-4115-8c93-bb472d6caa3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349293295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.2349293295
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.2069278757
Short name T418
Test name
Test status
Simulation time 46066859 ps
CPU time 1.79 seconds
Started May 23 12:43:29 PM PDT 24
Finished May 23 12:43:34 PM PDT 24
Peak memory 196216 kb
Host smart-87728fe9-4679-4ce3-9ced-b782247d470d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069278757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.2069278757
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.3674713168
Short name T17
Test name
Test status
Simulation time 87087813 ps
CPU time 0.98 seconds
Started May 23 12:43:18 PM PDT 24
Finished May 23 12:43:23 PM PDT 24
Peak memory 195680 kb
Host smart-a83b7ee3-55bf-4fec-9119-aaacbfbd741c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674713168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.3674713168
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.231841193
Short name T227
Test name
Test status
Simulation time 54475608 ps
CPU time 1.02 seconds
Started May 23 12:43:26 PM PDT 24
Finished May 23 12:43:30 PM PDT 24
Peak memory 196400 kb
Host smart-7abf9141-26c4-49a2-80bb-538fca1d3b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231841193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.231841193
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.401194234
Short name T281
Test name
Test status
Simulation time 42024447 ps
CPU time 1.05 seconds
Started May 23 12:43:30 PM PDT 24
Finished May 23 12:43:34 PM PDT 24
Peak memory 195872 kb
Host smart-33938ca0-8f40-4402-9f6b-e5e0f4ed1160
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401194234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullup
_pulldown.401194234
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.2313452680
Short name T297
Test name
Test status
Simulation time 286085499 ps
CPU time 2.4 seconds
Started May 23 12:43:25 PM PDT 24
Finished May 23 12:43:30 PM PDT 24
Peak memory 197968 kb
Host smart-e23b6496-6616-4fe9-88b5-24010a145494
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313452680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.2313452680
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.268373087
Short name T31
Test name
Test status
Simulation time 128045638 ps
CPU time 1.34 seconds
Started May 23 12:43:19 PM PDT 24
Finished May 23 12:43:24 PM PDT 24
Peak memory 196332 kb
Host smart-83cec2dc-6af6-49e1-94f0-6f4dc8534ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268373087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.268373087
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.3688925013
Short name T120
Test name
Test status
Simulation time 321114865 ps
CPU time 1.3 seconds
Started May 23 12:43:23 PM PDT 24
Finished May 23 12:43:27 PM PDT 24
Peak memory 195464 kb
Host smart-bfe00f73-b9cb-4611-a1af-ea5b6b929057
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688925013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.3688925013
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.3619088659
Short name T313
Test name
Test status
Simulation time 3447177255 ps
CPU time 49.89 seconds
Started May 23 12:43:18 PM PDT 24
Finished May 23 12:44:12 PM PDT 24
Peak memory 198008 kb
Host smart-eac92133-20ba-4b1e-90a4-6124f9073511
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619088659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.3619088659
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.1590683430
Short name T457
Test name
Test status
Simulation time 33962780 ps
CPU time 0.55 seconds
Started May 23 12:43:24 PM PDT 24
Finished May 23 12:43:28 PM PDT 24
Peak memory 193792 kb
Host smart-d86b547d-ce78-43d0-b0d2-bc22776a09b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590683430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.1590683430
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.1164064978
Short name T174
Test name
Test status
Simulation time 22513871 ps
CPU time 0.78 seconds
Started May 23 12:43:15 PM PDT 24
Finished May 23 12:43:17 PM PDT 24
Peak memory 195164 kb
Host smart-ea1be205-6416-4689-a89e-b4487711b4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164064978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.1164064978
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.2265194440
Short name T593
Test name
Test status
Simulation time 958652484 ps
CPU time 26.59 seconds
Started May 23 12:43:18 PM PDT 24
Finished May 23 12:43:48 PM PDT 24
Peak memory 196776 kb
Host smart-da8c92d8-dd01-4653-9a4d-b5cbec19444e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265194440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.2265194440
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.1518027641
Short name T617
Test name
Test status
Simulation time 44497206 ps
CPU time 0.84 seconds
Started May 23 12:43:18 PM PDT 24
Finished May 23 12:43:22 PM PDT 24
Peak memory 195712 kb
Host smart-b889549d-e83f-4424-b6e5-89a692797ae7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518027641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.1518027641
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.4095260033
Short name T503
Test name
Test status
Simulation time 191953395 ps
CPU time 1.16 seconds
Started May 23 12:43:17 PM PDT 24
Finished May 23 12:43:21 PM PDT 24
Peak memory 196460 kb
Host smart-ae4676b2-ca96-49e7-a786-c79430ce3964
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095260033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.4095260033
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.2140813769
Short name T507
Test name
Test status
Simulation time 160633828 ps
CPU time 2.38 seconds
Started May 23 12:43:24 PM PDT 24
Finished May 23 12:43:30 PM PDT 24
Peak memory 197936 kb
Host smart-79d149f5-7f58-4be3-b542-9cfe043dc8b7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140813769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.2140813769
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.2554374209
Short name T395
Test name
Test status
Simulation time 102193952 ps
CPU time 2.02 seconds
Started May 23 12:43:20 PM PDT 24
Finished May 23 12:43:25 PM PDT 24
Peak memory 195652 kb
Host smart-eb0cc5b0-92e4-4067-b62a-70b0830535a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554374209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.2554374209
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.2711730614
Short name T209
Test name
Test status
Simulation time 133455616 ps
CPU time 1.3 seconds
Started May 23 12:43:18 PM PDT 24
Finished May 23 12:43:23 PM PDT 24
Peak memory 195780 kb
Host smart-5f248ee7-7c6c-4bd0-be54-20769c276cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711730614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.2711730614
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.2192377344
Short name T415
Test name
Test status
Simulation time 78678277 ps
CPU time 1.08 seconds
Started May 23 12:43:16 PM PDT 24
Finished May 23 12:43:20 PM PDT 24
Peak memory 196016 kb
Host smart-2b04b576-4db2-44e0-8e10-279575857dad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192377344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.2192377344
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.3238521189
Short name T517
Test name
Test status
Simulation time 403648362 ps
CPU time 1.44 seconds
Started May 23 12:43:23 PM PDT 24
Finished May 23 12:43:28 PM PDT 24
Peak memory 197940 kb
Host smart-27f78725-f052-46c7-9a9d-daa571464899
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238521189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.3238521189
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.2799199981
Short name T30
Test name
Test status
Simulation time 33687972 ps
CPU time 0.94 seconds
Started May 23 12:43:16 PM PDT 24
Finished May 23 12:43:20 PM PDT 24
Peak memory 195688 kb
Host smart-ab44aa43-3f1f-40a7-9e5d-c39aac6bc6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799199981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.2799199981
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.4237078052
Short name T342
Test name
Test status
Simulation time 146840093 ps
CPU time 1.04 seconds
Started May 23 12:43:15 PM PDT 24
Finished May 23 12:43:18 PM PDT 24
Peak memory 196320 kb
Host smart-b437b669-2e0e-4416-bee1-adbe0c7297dc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237078052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.4237078052
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.1150489201
Short name T425
Test name
Test status
Simulation time 45802754512 ps
CPU time 144.88 seconds
Started May 23 12:43:17 PM PDT 24
Finished May 23 12:45:45 PM PDT 24
Peak memory 198116 kb
Host smart-b135f466-f0a3-4fad-8a76-874d07bb9f0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150489201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.1150489201
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.3718772925
Short name T557
Test name
Test status
Simulation time 15869535 ps
CPU time 0.61 seconds
Started May 23 12:43:27 PM PDT 24
Finished May 23 12:43:31 PM PDT 24
Peak memory 194884 kb
Host smart-18ded13e-1295-41fb-b4c0-213bf84e8fe6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718772925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.3718772925
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.1151359418
Short name T555
Test name
Test status
Simulation time 64968006 ps
CPU time 0.73 seconds
Started May 23 12:43:34 PM PDT 24
Finished May 23 12:43:37 PM PDT 24
Peak memory 195748 kb
Host smart-7b964651-d99a-411b-aec2-3092fb524e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151359418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.1151359418
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.3055275282
Short name T441
Test name
Test status
Simulation time 504043684 ps
CPU time 14.56 seconds
Started May 23 12:43:31 PM PDT 24
Finished May 23 12:43:49 PM PDT 24
Peak memory 195348 kb
Host smart-8914eac3-b1cc-4329-9424-117b501106c8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055275282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.3055275282
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.4024376906
Short name T501
Test name
Test status
Simulation time 59282336 ps
CPU time 0.96 seconds
Started May 23 12:43:29 PM PDT 24
Finished May 23 12:43:33 PM PDT 24
Peak memory 197080 kb
Host smart-f03e2a8b-c3f4-448a-9840-b53a3159e3a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024376906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.4024376906
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.4114093776
Short name T134
Test name
Test status
Simulation time 44536902 ps
CPU time 1.2 seconds
Started May 23 12:43:36 PM PDT 24
Finished May 23 12:43:40 PM PDT 24
Peak memory 197148 kb
Host smart-42e29e62-9392-4b19-af32-1aacf12b1e1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114093776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.4114093776
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.3494640767
Short name T220
Test name
Test status
Simulation time 363636046 ps
CPU time 3.15 seconds
Started May 23 12:43:47 PM PDT 24
Finished May 23 12:43:53 PM PDT 24
Peak memory 198012 kb
Host smart-9bc7aa12-69cf-406a-a16c-dc99d9459d78
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494640767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.3494640767
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.2825048829
Short name T566
Test name
Test status
Simulation time 123403200 ps
CPU time 3.54 seconds
Started May 23 12:43:46 PM PDT 24
Finished May 23 12:43:52 PM PDT 24
Peak memory 197036 kb
Host smart-28301a96-f64a-4b9e-9af6-50a9affa8a46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825048829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.2825048829
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.4002968578
Short name T335
Test name
Test status
Simulation time 100971982 ps
CPU time 1 seconds
Started May 23 12:43:36 PM PDT 24
Finished May 23 12:43:40 PM PDT 24
Peak memory 195692 kb
Host smart-3e3ba07b-61cc-4544-99b5-06555e0cf034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002968578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.4002968578
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.1763487844
Short name T203
Test name
Test status
Simulation time 29795824 ps
CPU time 1.11 seconds
Started May 23 12:43:28 PM PDT 24
Finished May 23 12:43:33 PM PDT 24
Peak memory 196552 kb
Host smart-c53ba28e-9312-4d6e-be43-6011c9e03417
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763487844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.1763487844
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.3185422924
Short name T271
Test name
Test status
Simulation time 101917192 ps
CPU time 4.33 seconds
Started May 23 12:43:29 PM PDT 24
Finished May 23 12:43:37 PM PDT 24
Peak memory 197908 kb
Host smart-bcc7d519-c24c-40af-a4dc-9e1ebe5ffe56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185422924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.3185422924
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.2378965432
Short name T194
Test name
Test status
Simulation time 416758027 ps
CPU time 1.48 seconds
Started May 23 12:43:16 PM PDT 24
Finished May 23 12:43:21 PM PDT 24
Peak memory 195492 kb
Host smart-f4be05c6-7ffb-4840-a1dd-0b641ed6fc11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378965432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.2378965432
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.644260225
Short name T454
Test name
Test status
Simulation time 206086244 ps
CPU time 1.5 seconds
Started May 23 12:43:18 PM PDT 24
Finished May 23 12:43:23 PM PDT 24
Peak memory 196624 kb
Host smart-0f8a91b9-aa3a-4b84-adff-98dde5805183
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644260225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.644260225
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.1662377512
Short name T320
Test name
Test status
Simulation time 6715764808 ps
CPU time 170.15 seconds
Started May 23 12:43:31 PM PDT 24
Finished May 23 12:46:24 PM PDT 24
Peak memory 198196 kb
Host smart-fb37079f-7653-4497-a7c8-2e6a397fa38b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662377512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.1662377512
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.3586652804
Short name T424
Test name
Test status
Simulation time 19401895 ps
CPU time 0.56 seconds
Started May 23 12:43:35 PM PDT 24
Finished May 23 12:43:38 PM PDT 24
Peak memory 193748 kb
Host smart-75f56c82-3b3a-42b3-bdbf-d3566499d1fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586652804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.3586652804
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.2910211299
Short name T201
Test name
Test status
Simulation time 74303862 ps
CPU time 0.68 seconds
Started May 23 12:43:30 PM PDT 24
Finished May 23 12:43:34 PM PDT 24
Peak memory 194268 kb
Host smart-eb406b17-18b4-4f9b-878e-8507169aa38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910211299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.2910211299
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.36237281
Short name T77
Test name
Test status
Simulation time 254640790 ps
CPU time 12.62 seconds
Started May 23 12:43:34 PM PDT 24
Finished May 23 12:43:49 PM PDT 24
Peak memory 196700 kb
Host smart-cd22abbc-7a03-468a-82e0-edcfe842a6a4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36237281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stress
.36237281
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.1919414940
Short name T695
Test name
Test status
Simulation time 359070315 ps
CPU time 0.83 seconds
Started May 23 12:43:32 PM PDT 24
Finished May 23 12:43:35 PM PDT 24
Peak memory 195924 kb
Host smart-cb298a43-829e-43a9-a869-c5429f954507
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919414940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.1919414940
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.2109540583
Short name T379
Test name
Test status
Simulation time 55797731 ps
CPU time 1.02 seconds
Started May 23 12:43:30 PM PDT 24
Finished May 23 12:43:34 PM PDT 24
Peak memory 195676 kb
Host smart-400aadc4-9e70-495b-8296-5cf8375945c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109540583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.2109540583
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.866839173
Short name T237
Test name
Test status
Simulation time 245277649 ps
CPU time 2.4 seconds
Started May 23 12:43:29 PM PDT 24
Finished May 23 12:43:35 PM PDT 24
Peak memory 197952 kb
Host smart-1c01a944-dff1-4cab-8174-4cd6f7700bf4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866839173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.gpio_intr_with_filter_rand_intr_event.866839173
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.3364560362
Short name T253
Test name
Test status
Simulation time 220658583 ps
CPU time 3.4 seconds
Started May 23 12:43:28 PM PDT 24
Finished May 23 12:43:35 PM PDT 24
Peak memory 197056 kb
Host smart-35bb6878-ae8e-49c6-b6bc-1bcebc6bf9ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364560362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.3364560362
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.4198554875
Short name T143
Test name
Test status
Simulation time 27852726 ps
CPU time 0.97 seconds
Started May 23 12:43:38 PM PDT 24
Finished May 23 12:43:40 PM PDT 24
Peak memory 196516 kb
Host smart-ca23679b-d2eb-479b-a493-71b7602e260c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198554875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.4198554875
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.2973724176
Short name T27
Test name
Test status
Simulation time 214542944 ps
CPU time 1.03 seconds
Started May 23 12:43:27 PM PDT 24
Finished May 23 12:43:31 PM PDT 24
Peak memory 196588 kb
Host smart-ff0062f5-cbd7-4e1e-8b3a-7104e3c001ad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973724176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.2973724176
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.2888884358
Short name T217
Test name
Test status
Simulation time 118179231 ps
CPU time 1.45 seconds
Started May 23 12:43:44 PM PDT 24
Finished May 23 12:43:47 PM PDT 24
Peak memory 197808 kb
Host smart-e5c193f6-ffe3-4c6e-b0e6-dd14c4a4de1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888884358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.2888884358
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.831851723
Short name T257
Test name
Test status
Simulation time 51088173 ps
CPU time 1.35 seconds
Started May 23 12:43:28 PM PDT 24
Finished May 23 12:43:33 PM PDT 24
Peak memory 196460 kb
Host smart-0f8e6224-7415-483a-9b00-cb5dd9eb6d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831851723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.831851723
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.3485422907
Short name T649
Test name
Test status
Simulation time 42112389 ps
CPU time 1.06 seconds
Started May 23 12:43:34 PM PDT 24
Finished May 23 12:43:37 PM PDT 24
Peak memory 195516 kb
Host smart-3ba237b0-544c-49ea-b439-f0d42abd08b4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485422907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.3485422907
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.3862654292
Short name T687
Test name
Test status
Simulation time 6204037424 ps
CPU time 74.77 seconds
Started May 23 12:43:48 PM PDT 24
Finished May 23 12:45:05 PM PDT 24
Peak memory 198124 kb
Host smart-4b6071d4-5d35-4934-a6cf-6e0f40ccf689
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862654292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.3862654292
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.1776103893
Short name T690
Test name
Test status
Simulation time 646383957758 ps
CPU time 1887.09 seconds
Started May 23 12:43:37 PM PDT 24
Finished May 23 01:15:06 PM PDT 24
Peak memory 198248 kb
Host smart-a78f0a49-05f1-4bd7-96c7-b5499a3aa409
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1776103893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.1776103893
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.2828103821
Short name T388
Test name
Test status
Simulation time 35689088 ps
CPU time 0.64 seconds
Started May 23 12:43:30 PM PDT 24
Finished May 23 12:43:34 PM PDT 24
Peak memory 194080 kb
Host smart-b1abff8b-706b-4550-ab41-a090092817ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828103821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.2828103821
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.3916845005
Short name T74
Test name
Test status
Simulation time 63022249 ps
CPU time 0.73 seconds
Started May 23 12:43:28 PM PDT 24
Finished May 23 12:43:32 PM PDT 24
Peak memory 195068 kb
Host smart-f7ebd94b-9898-4aec-9322-366f3c2a4ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916845005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.3916845005
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.3041147221
Short name T159
Test name
Test status
Simulation time 803942556 ps
CPU time 9.89 seconds
Started May 23 12:43:30 PM PDT 24
Finished May 23 12:43:43 PM PDT 24
Peak memory 197940 kb
Host smart-c2f0a3c4-519a-437a-a312-c9aaf0d54b72
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041147221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.3041147221
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.2386854173
Short name T5
Test name
Test status
Simulation time 188392293 ps
CPU time 0.71 seconds
Started May 23 12:43:46 PM PDT 24
Finished May 23 12:43:49 PM PDT 24
Peak memory 194632 kb
Host smart-7448709e-5f59-48fb-8a14-a41f0810816f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386854173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.2386854173
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.1946747837
Short name T586
Test name
Test status
Simulation time 77641836 ps
CPU time 1.26 seconds
Started May 23 12:43:29 PM PDT 24
Finished May 23 12:43:33 PM PDT 24
Peak memory 197332 kb
Host smart-52d0e5a2-76e9-4988-804b-1ffaf338adf9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946747837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.1946747837
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.1739598043
Short name T543
Test name
Test status
Simulation time 61917075 ps
CPU time 2.63 seconds
Started May 23 12:43:31 PM PDT 24
Finished May 23 12:43:37 PM PDT 24
Peak memory 197936 kb
Host smart-1f9d18e8-877b-4aeb-9da9-13ffeaf8208d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739598043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.1739598043
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.1075222122
Short name T173
Test name
Test status
Simulation time 41148928 ps
CPU time 1.16 seconds
Started May 23 12:43:32 PM PDT 24
Finished May 23 12:43:36 PM PDT 24
Peak memory 196324 kb
Host smart-88c7d9cf-9433-4ab8-95a3-9cc3ef83bd4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075222122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.1075222122
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.3366465506
Short name T412
Test name
Test status
Simulation time 119699132 ps
CPU time 1.21 seconds
Started May 23 12:43:46 PM PDT 24
Finished May 23 12:43:48 PM PDT 24
Peak memory 198032 kb
Host smart-e5759473-a29a-4786-9dea-8d0fe4564972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366465506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.3366465506
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.142442746
Short name T655
Test name
Test status
Simulation time 107960552 ps
CPU time 0.99 seconds
Started May 23 12:43:28 PM PDT 24
Finished May 23 12:43:32 PM PDT 24
Peak memory 195904 kb
Host smart-b996d6d1-7538-4988-a9da-0f3b22491929
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142442746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullup
_pulldown.142442746
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.2771404821
Short name T452
Test name
Test status
Simulation time 569227930 ps
CPU time 4.27 seconds
Started May 23 12:43:26 PM PDT 24
Finished May 23 12:43:33 PM PDT 24
Peak memory 197876 kb
Host smart-0313f733-f317-452d-b64a-e1013114253f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771404821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.2771404821
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.2260689582
Short name T692
Test name
Test status
Simulation time 172822586 ps
CPU time 1.41 seconds
Started May 23 12:43:28 PM PDT 24
Finished May 23 12:43:32 PM PDT 24
Peak memory 196608 kb
Host smart-ea3ea36d-0e68-464a-8956-95d83e4f38d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260689582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.2260689582
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.2105008262
Short name T620
Test name
Test status
Simulation time 86872330 ps
CPU time 0.83 seconds
Started May 23 12:43:31 PM PDT 24
Finished May 23 12:43:35 PM PDT 24
Peak memory 195208 kb
Host smart-e5846c26-2a99-4a90-9943-6946f937d407
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105008262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.2105008262
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.2421157620
Short name T619
Test name
Test status
Simulation time 9289577814 ps
CPU time 61.26 seconds
Started May 23 12:43:33 PM PDT 24
Finished May 23 12:44:37 PM PDT 24
Peak memory 197948 kb
Host smart-9c9528b1-0794-4a76-b4b8-7c12580895ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421157620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.2421157620
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.3316137854
Short name T286
Test name
Test status
Simulation time 13361636 ps
CPU time 0.58 seconds
Started May 23 12:43:32 PM PDT 24
Finished May 23 12:43:36 PM PDT 24
Peak memory 194060 kb
Host smart-100a5982-08d3-4f68-a231-a0a6c97ff119
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316137854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.3316137854
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.1416191161
Short name T421
Test name
Test status
Simulation time 38531624 ps
CPU time 0.8 seconds
Started May 23 12:43:26 PM PDT 24
Finished May 23 12:43:29 PM PDT 24
Peak memory 195244 kb
Host smart-742cc857-a0da-4644-95d9-b3660251ab48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416191161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.1416191161
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.3522998540
Short name T600
Test name
Test status
Simulation time 1113381909 ps
CPU time 15.91 seconds
Started May 23 12:43:28 PM PDT 24
Finished May 23 12:43:47 PM PDT 24
Peak memory 196712 kb
Host smart-b3b03813-c655-4513-b888-47464606de89
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522998540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.3522998540
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.204337331
Short name T406
Test name
Test status
Simulation time 80603568 ps
CPU time 1.01 seconds
Started May 23 12:43:28 PM PDT 24
Finished May 23 12:43:32 PM PDT 24
Peak memory 196564 kb
Host smart-bee6fba0-65b0-4958-a225-ce64b7498fdc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204337331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.204337331
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.876965261
Short name T515
Test name
Test status
Simulation time 23033508 ps
CPU time 0.66 seconds
Started May 23 12:43:38 PM PDT 24
Finished May 23 12:43:40 PM PDT 24
Peak memory 194360 kb
Host smart-52aaa3a5-3ac0-47b3-9aa5-f32b8268dea0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876965261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.876965261
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.2187360999
Short name T137
Test name
Test status
Simulation time 46249516 ps
CPU time 1.89 seconds
Started May 23 12:43:31 PM PDT 24
Finished May 23 12:43:36 PM PDT 24
Peak memory 197896 kb
Host smart-83d698c1-121e-4207-8c1e-1ec484fe67b2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187360999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.2187360999
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.2987749087
Short name T172
Test name
Test status
Simulation time 381042473 ps
CPU time 2.4 seconds
Started May 23 12:43:31 PM PDT 24
Finished May 23 12:43:36 PM PDT 24
Peak memory 195776 kb
Host smart-01336dc2-13b8-4963-91e8-7be0fc276ff5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987749087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.2987749087
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.2979227703
Short name T429
Test name
Test status
Simulation time 62616227 ps
CPU time 1.24 seconds
Started May 23 12:43:28 PM PDT 24
Finished May 23 12:43:32 PM PDT 24
Peak memory 197980 kb
Host smart-bdd4bfef-8f56-41f7-8820-3e561be95608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979227703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.2979227703
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.458477456
Short name T477
Test name
Test status
Simulation time 95597111 ps
CPU time 0.79 seconds
Started May 23 12:43:33 PM PDT 24
Finished May 23 12:43:36 PM PDT 24
Peak memory 195440 kb
Host smart-716365a6-c84a-444d-a9a6-a9ada6c4273a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458477456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullup
_pulldown.458477456
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.333554524
Short name T310
Test name
Test status
Simulation time 399017668 ps
CPU time 2.64 seconds
Started May 23 12:43:28 PM PDT 24
Finished May 23 12:43:34 PM PDT 24
Peak memory 197824 kb
Host smart-f0da4983-f79f-4684-a744-a35a8c30e9b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333554524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ran
dom_long_reg_writes_reg_reads.333554524
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.964987126
Short name T349
Test name
Test status
Simulation time 310120413 ps
CPU time 1.36 seconds
Started May 23 12:43:38 PM PDT 24
Finished May 23 12:43:41 PM PDT 24
Peak memory 197972 kb
Host smart-7915067a-777a-4d0a-b0a0-ee2f2d9033c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964987126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.964987126
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.3068922516
Short name T594
Test name
Test status
Simulation time 157996404 ps
CPU time 0.93 seconds
Started May 23 12:43:30 PM PDT 24
Finished May 23 12:43:34 PM PDT 24
Peak memory 196224 kb
Host smart-271214dc-52a3-4955-9dc2-bdbc5518ad4c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068922516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.3068922516
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.1407004323
Short name T528
Test name
Test status
Simulation time 4257310235 ps
CPU time 109.9 seconds
Started May 23 12:43:29 PM PDT 24
Finished May 23 12:45:22 PM PDT 24
Peak memory 198084 kb
Host smart-2bc2c509-6c90-4bc2-91a7-400bb501ff6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407004323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.1407004323
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.3618287327
Short name T554
Test name
Test status
Simulation time 76055729 ps
CPU time 0.57 seconds
Started May 23 12:43:35 PM PDT 24
Finished May 23 12:43:38 PM PDT 24
Peak memory 193780 kb
Host smart-bfc5ae80-f7b1-426d-9e2b-4b5287c2a7c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618287327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.3618287327
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.673960002
Short name T396
Test name
Test status
Simulation time 51505850 ps
CPU time 0.92 seconds
Started May 23 12:43:46 PM PDT 24
Finished May 23 12:43:48 PM PDT 24
Peak memory 195596 kb
Host smart-1a033a08-4ec6-499f-9d8f-3bf3b8227398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673960002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.673960002
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.3304502369
Short name T363
Test name
Test status
Simulation time 755550474 ps
CPU time 23.96 seconds
Started May 23 12:43:36 PM PDT 24
Finished May 23 12:44:03 PM PDT 24
Peak memory 195444 kb
Host smart-421d220d-101d-42dc-ba55-974041405077
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304502369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.3304502369
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.3666235635
Short name T80
Test name
Test status
Simulation time 157711055 ps
CPU time 0.78 seconds
Started May 23 12:43:34 PM PDT 24
Finished May 23 12:43:37 PM PDT 24
Peak memory 195708 kb
Host smart-62d81f03-81c5-4beb-bd6e-eacd1deda0c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666235635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.3666235635
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.913287216
Short name T526
Test name
Test status
Simulation time 1308612544 ps
CPU time 1.39 seconds
Started May 23 12:43:26 PM PDT 24
Finished May 23 12:43:31 PM PDT 24
Peak memory 196916 kb
Host smart-9a2f8bda-f002-4ba6-b2aa-ad52d0f04fda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913287216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.913287216
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.3747701175
Short name T231
Test name
Test status
Simulation time 180787954 ps
CPU time 3.14 seconds
Started May 23 12:43:37 PM PDT 24
Finished May 23 12:43:42 PM PDT 24
Peak memory 198056 kb
Host smart-98efd0c1-59d2-4458-9b1e-a935d9562a76
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747701175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.3747701175
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.1676744663
Short name T485
Test name
Test status
Simulation time 105036197 ps
CPU time 3 seconds
Started May 23 12:43:40 PM PDT 24
Finished May 23 12:43:44 PM PDT 24
Peak memory 195756 kb
Host smart-f8243c5c-52fc-4503-ba8d-3008d3fc51d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676744663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.1676744663
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.1848140871
Short name T181
Test name
Test status
Simulation time 73494301 ps
CPU time 0.97 seconds
Started May 23 12:43:49 PM PDT 24
Finished May 23 12:43:52 PM PDT 24
Peak memory 195748 kb
Host smart-4d38754e-b0cd-4c59-801d-7ea78bda0577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848140871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.1848140871
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.2638847527
Short name T128
Test name
Test status
Simulation time 223642324 ps
CPU time 1.22 seconds
Started May 23 12:43:38 PM PDT 24
Finished May 23 12:43:40 PM PDT 24
Peak memory 196544 kb
Host smart-0ea98606-f6cf-4a84-901d-ab44a700d2d7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638847527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.2638847527
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.856215737
Short name T492
Test name
Test status
Simulation time 186192962 ps
CPU time 2.68 seconds
Started May 23 12:43:35 PM PDT 24
Finished May 23 12:43:40 PM PDT 24
Peak memory 197912 kb
Host smart-054775c1-4ef7-415e-a72b-78cec5e956db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856215737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ran
dom_long_reg_writes_reg_reads.856215737
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.2622984764
Short name T321
Test name
Test status
Simulation time 77523824 ps
CPU time 1.2 seconds
Started May 23 12:43:46 PM PDT 24
Finished May 23 12:43:50 PM PDT 24
Peak memory 195732 kb
Host smart-0a331f31-3172-46df-8320-05b0dd772bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622984764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.2622984764
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.2137616994
Short name T381
Test name
Test status
Simulation time 71664248 ps
CPU time 1.12 seconds
Started May 23 12:43:36 PM PDT 24
Finished May 23 12:43:40 PM PDT 24
Peak memory 195464 kb
Host smart-884ab035-b05c-47eb-a596-eede799f39c7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137616994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.2137616994
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.1963673296
Short name T491
Test name
Test status
Simulation time 19659620584 ps
CPU time 103.5 seconds
Started May 23 12:43:29 PM PDT 24
Finished May 23 12:45:16 PM PDT 24
Peak memory 198048 kb
Host smart-a2d3dea9-90eb-494c-bd85-931c35a4a74d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963673296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.1963673296
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.1153712284
Short name T433
Test name
Test status
Simulation time 17883832 ps
CPU time 0.54 seconds
Started May 23 12:43:43 PM PDT 24
Finished May 23 12:43:44 PM PDT 24
Peak memory 193772 kb
Host smart-1bf46c66-7216-4c1e-9dc9-c6e0e1d3e3cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153712284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.1153712284
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.3032720769
Short name T122
Test name
Test status
Simulation time 105378167 ps
CPU time 0.9 seconds
Started May 23 12:43:45 PM PDT 24
Finished May 23 12:43:48 PM PDT 24
Peak memory 195624 kb
Host smart-27fdd845-1930-43f9-b3d3-a835a8a507ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032720769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.3032720769
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.87640776
Short name T351
Test name
Test status
Simulation time 799088763 ps
CPU time 26.55 seconds
Started May 23 12:43:32 PM PDT 24
Finished May 23 12:44:01 PM PDT 24
Peak memory 197844 kb
Host smart-0aa3dc5d-4e13-4f52-bfc5-f9300e54a08a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87640776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stress
.87640776
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.2462416232
Short name T402
Test name
Test status
Simulation time 33624350 ps
CPU time 0.67 seconds
Started May 23 12:43:48 PM PDT 24
Finished May 23 12:43:51 PM PDT 24
Peak memory 194596 kb
Host smart-05b8f271-39de-47ba-b493-9e632778bf63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462416232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.2462416232
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.2835606890
Short name T686
Test name
Test status
Simulation time 84047195 ps
CPU time 0.75 seconds
Started May 23 12:43:30 PM PDT 24
Finished May 23 12:43:34 PM PDT 24
Peak memory 195308 kb
Host smart-eaf2f049-f35e-42ee-8372-b1b7392691e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835606890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.2835606890
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.4162429560
Short name T276
Test name
Test status
Simulation time 40599684 ps
CPU time 1.6 seconds
Started May 23 12:43:37 PM PDT 24
Finished May 23 12:43:41 PM PDT 24
Peak memory 196740 kb
Host smart-d83a6edb-20dd-4b6e-b14e-cc536c7206cd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162429560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.4162429560
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.3898548850
Short name T488
Test name
Test status
Simulation time 267620454 ps
CPU time 1.52 seconds
Started May 23 12:43:36 PM PDT 24
Finished May 23 12:43:40 PM PDT 24
Peak memory 196432 kb
Host smart-2ab7e4c2-a41b-4578-b166-84438686415d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898548850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.3898548850
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.1061143951
Short name T118
Test name
Test status
Simulation time 753385107 ps
CPU time 0.91 seconds
Started May 23 12:43:32 PM PDT 24
Finished May 23 12:43:36 PM PDT 24
Peak memory 195916 kb
Host smart-370a1f3b-ca12-48bf-8697-496778d61743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061143951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.1061143951
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.3929891231
Short name T414
Test name
Test status
Simulation time 69337243 ps
CPU time 1.21 seconds
Started May 23 12:43:49 PM PDT 24
Finished May 23 12:43:52 PM PDT 24
Peak memory 196868 kb
Host smart-5e3dd97a-95c9-4c09-a9f2-0aba09cbbf7c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929891231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.3929891231
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.1523341888
Short name T73
Test name
Test status
Simulation time 262688859 ps
CPU time 2.98 seconds
Started May 23 12:43:34 PM PDT 24
Finished May 23 12:43:40 PM PDT 24
Peak memory 197808 kb
Host smart-3b211508-79d0-42a1-a5b0-4292c35cda5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523341888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.1523341888
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.4291197863
Short name T200
Test name
Test status
Simulation time 245505304 ps
CPU time 1.15 seconds
Started May 23 12:43:34 PM PDT 24
Finished May 23 12:43:37 PM PDT 24
Peak memory 196288 kb
Host smart-f4e33383-5de2-4000-86db-0a601bb15e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291197863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.4291197863
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.3397850695
Short name T213
Test name
Test status
Simulation time 126595215 ps
CPU time 1.06 seconds
Started May 23 12:43:30 PM PDT 24
Finished May 23 12:43:34 PM PDT 24
Peak memory 195664 kb
Host smart-e0b97d50-d69b-482a-b885-4f284dd01b65
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397850695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.3397850695
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.218988699
Short name T625
Test name
Test status
Simulation time 21908129406 ps
CPU time 116.67 seconds
Started May 23 12:43:49 PM PDT 24
Finished May 23 12:45:48 PM PDT 24
Peak memory 198080 kb
Host smart-a6994488-5924-4b53-88c6-d5c3ef02a864
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218988699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.g
pio_stress_all.218988699
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.1711971960
Short name T68
Test name
Test status
Simulation time 584229549696 ps
CPU time 943.7 seconds
Started May 23 12:43:41 PM PDT 24
Finished May 23 12:59:25 PM PDT 24
Peak memory 206208 kb
Host smart-1443f801-4393-4c44-9697-756536d31805
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1711971960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.1711971960
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.705336986
Short name T420
Test name
Test status
Simulation time 30500463 ps
CPU time 0.55 seconds
Started May 23 12:43:52 PM PDT 24
Finished May 23 12:43:54 PM PDT 24
Peak memory 192624 kb
Host smart-31895119-c59e-409a-beb6-94c71b3f662d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705336986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.705336986
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.985621907
Short name T162
Test name
Test status
Simulation time 19992024 ps
CPU time 0.74 seconds
Started May 23 12:43:44 PM PDT 24
Finished May 23 12:43:46 PM PDT 24
Peak memory 195344 kb
Host smart-09d187c4-26b7-4e63-a5ac-77baccb56f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985621907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.985621907
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.841506403
Short name T296
Test name
Test status
Simulation time 201518308 ps
CPU time 7.87 seconds
Started May 23 12:43:51 PM PDT 24
Finished May 23 12:44:00 PM PDT 24
Peak memory 196704 kb
Host smart-14a08205-7d32-48e4-ad73-9a9be81eee83
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841506403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stres
s.841506403
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.4257958592
Short name T631
Test name
Test status
Simulation time 345223497 ps
CPU time 1.06 seconds
Started May 23 12:43:46 PM PDT 24
Finished May 23 12:43:48 PM PDT 24
Peak memory 196548 kb
Host smart-a2725f66-661d-4f42-a062-db04b010937f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257958592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.4257958592
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.1024019740
Short name T573
Test name
Test status
Simulation time 86682657 ps
CPU time 1.26 seconds
Started May 23 12:43:49 PM PDT 24
Finished May 23 12:43:52 PM PDT 24
Peak memory 197264 kb
Host smart-225b7a22-4c3e-42a4-813c-c98b259c0b3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024019740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.1024019740
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.1428555334
Short name T456
Test name
Test status
Simulation time 107714745 ps
CPU time 1.58 seconds
Started May 23 12:43:50 PM PDT 24
Finished May 23 12:43:54 PM PDT 24
Peak memory 196632 kb
Host smart-5cb0dde8-1f71-4437-954a-652113e0cf35
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428555334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.1428555334
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.3377937502
Short name T430
Test name
Test status
Simulation time 34107923 ps
CPU time 1.01 seconds
Started May 23 12:43:48 PM PDT 24
Finished May 23 12:43:51 PM PDT 24
Peak memory 195580 kb
Host smart-7cc14867-ec54-4bc5-8a98-d229aeafd58c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377937502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.3377937502
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.1054622092
Short name T196
Test name
Test status
Simulation time 57805060 ps
CPU time 1.11 seconds
Started May 23 12:43:46 PM PDT 24
Finished May 23 12:43:50 PM PDT 24
Peak memory 196420 kb
Host smart-25ca72d8-577f-49dd-bb95-83b2cfd43070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054622092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.1054622092
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.2853757426
Short name T678
Test name
Test status
Simulation time 285702704 ps
CPU time 0.83 seconds
Started May 23 12:43:41 PM PDT 24
Finished May 23 12:43:42 PM PDT 24
Peak memory 196512 kb
Host smart-bbda6c8e-924e-465c-9062-ffb6a7d56b84
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853757426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.2853757426
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.2611163979
Short name T218
Test name
Test status
Simulation time 84051639 ps
CPU time 1.77 seconds
Started May 23 12:43:46 PM PDT 24
Finished May 23 12:43:49 PM PDT 24
Peak memory 197816 kb
Host smart-d1a5dd5e-f42a-473b-be31-9dfa78b6e4d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611163979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.2611163979
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.3772811930
Short name T358
Test name
Test status
Simulation time 47410652 ps
CPU time 1.01 seconds
Started May 23 12:43:46 PM PDT 24
Finished May 23 12:43:49 PM PDT 24
Peak memory 195620 kb
Host smart-55afeb18-4c3d-4561-9097-f1e9a357a0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772811930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.3772811930
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.2042223350
Short name T705
Test name
Test status
Simulation time 71396004 ps
CPU time 0.95 seconds
Started May 23 12:43:46 PM PDT 24
Finished May 23 12:43:48 PM PDT 24
Peak memory 196568 kb
Host smart-7846a666-954a-4e0f-9244-1a7fce4d9811
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042223350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.2042223350
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.3371242274
Short name T326
Test name
Test status
Simulation time 77819704928 ps
CPU time 83.03 seconds
Started May 23 12:43:51 PM PDT 24
Finished May 23 12:45:16 PM PDT 24
Peak memory 198112 kb
Host smart-7f451e49-b816-4d57-afb1-6fd584970111
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371242274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.3371242274
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.101311857
Short name T212
Test name
Test status
Simulation time 13332606 ps
CPU time 0.58 seconds
Started May 23 12:43:44 PM PDT 24
Finished May 23 12:43:45 PM PDT 24
Peak memory 193748 kb
Host smart-7c96991e-93bc-459a-aec7-7769c0f78094
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101311857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.101311857
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.1458944513
Short name T706
Test name
Test status
Simulation time 17423374 ps
CPU time 0.6 seconds
Started May 23 12:43:49 PM PDT 24
Finished May 23 12:43:52 PM PDT 24
Peak memory 193824 kb
Host smart-f200ecc9-32f7-4449-a897-2702b3f44b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458944513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.1458944513
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.3574366921
Short name T451
Test name
Test status
Simulation time 557405979 ps
CPU time 17.63 seconds
Started May 23 12:43:41 PM PDT 24
Finished May 23 12:43:59 PM PDT 24
Peak memory 197888 kb
Host smart-4f2b67f2-4376-4d40-b572-5f3838063aa0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574366921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.3574366921
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.1907279326
Short name T3
Test name
Test status
Simulation time 259082631 ps
CPU time 1.05 seconds
Started May 23 12:43:46 PM PDT 24
Finished May 23 12:43:50 PM PDT 24
Peak memory 196504 kb
Host smart-e8550d94-748a-4e1f-96c5-87a3ff3ce83b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907279326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.1907279326
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.3235565606
Short name T119
Test name
Test status
Simulation time 151215142 ps
CPU time 0.9 seconds
Started May 23 12:43:47 PM PDT 24
Finished May 23 12:43:50 PM PDT 24
Peak memory 197288 kb
Host smart-acdb3bbb-81bd-4c94-aa2d-ad295aeec6a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235565606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.3235565606
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.1259018530
Short name T582
Test name
Test status
Simulation time 172332401 ps
CPU time 2.95 seconds
Started May 23 12:43:44 PM PDT 24
Finished May 23 12:43:48 PM PDT 24
Peak memory 196368 kb
Host smart-75b7881d-733d-40c5-872a-4ab2894b7b1b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259018530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.1259018530
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.2170300610
Short name T672
Test name
Test status
Simulation time 67033303 ps
CPU time 1.83 seconds
Started May 23 12:43:47 PM PDT 24
Finished May 23 12:43:51 PM PDT 24
Peak memory 196888 kb
Host smart-3d4f943b-ea02-4f47-89a5-680cf3b5b43f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170300610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.2170300610
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.346224351
Short name T502
Test name
Test status
Simulation time 23580687 ps
CPU time 0.86 seconds
Started May 23 12:43:47 PM PDT 24
Finished May 23 12:43:50 PM PDT 24
Peak memory 195664 kb
Host smart-b399aec2-452b-4969-96ba-5ae6407021cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346224351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.346224351
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.1298915789
Short name T701
Test name
Test status
Simulation time 468683298 ps
CPU time 1.3 seconds
Started May 23 12:43:53 PM PDT 24
Finished May 23 12:43:56 PM PDT 24
Peak memory 195844 kb
Host smart-b68fd3bb-582e-4dfd-9c5c-f9f2577fe16f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298915789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.1298915789
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.2859675993
Short name T175
Test name
Test status
Simulation time 374159600 ps
CPU time 1.73 seconds
Started May 23 12:43:53 PM PDT 24
Finished May 23 12:43:55 PM PDT 24
Peak memory 197844 kb
Host smart-77e48213-d89e-433f-9e6b-996ce65159c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859675993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.2859675993
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.1255098720
Short name T289
Test name
Test status
Simulation time 255684238 ps
CPU time 1.01 seconds
Started May 23 12:43:44 PM PDT 24
Finished May 23 12:43:47 PM PDT 24
Peak memory 195620 kb
Host smart-c413f11c-b727-4028-97d5-691ad6b88028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255098720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.1255098720
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.2415203652
Short name T372
Test name
Test status
Simulation time 93340928 ps
CPU time 0.79 seconds
Started May 23 12:43:49 PM PDT 24
Finished May 23 12:43:52 PM PDT 24
Peak memory 196032 kb
Host smart-af834fff-eab0-4dc3-8b48-a5645e9cad90
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415203652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.2415203652
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.3553581417
Short name T523
Test name
Test status
Simulation time 13845681398 ps
CPU time 191.64 seconds
Started May 23 12:43:46 PM PDT 24
Finished May 23 12:47:00 PM PDT 24
Peak memory 198028 kb
Host smart-defc8400-7fd9-4f07-871a-ec79ca696b41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553581417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.3553581417
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.1072371710
Short name T70
Test name
Test status
Simulation time 158110856195 ps
CPU time 1987.19 seconds
Started May 23 12:43:50 PM PDT 24
Finished May 23 01:16:59 PM PDT 24
Peak memory 198136 kb
Host smart-1e9e3c42-e577-4b9f-80c9-783213f41d57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1072371710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.1072371710
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.1003104028
Short name T380
Test name
Test status
Simulation time 19963625 ps
CPU time 0.59 seconds
Started May 23 12:42:03 PM PDT 24
Finished May 23 12:42:05 PM PDT 24
Peak memory 193736 kb
Host smart-df71a8ae-0239-4456-8f5e-8d6da99cb683
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003104028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.1003104028
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.4243430821
Short name T673
Test name
Test status
Simulation time 76916342 ps
CPU time 0.83 seconds
Started May 23 12:42:01 PM PDT 24
Finished May 23 12:42:04 PM PDT 24
Peak memory 195176 kb
Host smart-82bcf964-6637-421f-a40e-a9c4fa5c5fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243430821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.4243430821
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.1515860234
Short name T364
Test name
Test status
Simulation time 3586358816 ps
CPU time 28.11 seconds
Started May 23 12:42:02 PM PDT 24
Finished May 23 12:42:31 PM PDT 24
Peak memory 197960 kb
Host smart-ffe75450-e21d-4d59-bcdb-b46b42a2f8e5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515860234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.1515860234
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.3306459418
Short name T8
Test name
Test status
Simulation time 103197310 ps
CPU time 0.84 seconds
Started May 23 12:42:05 PM PDT 24
Finished May 23 12:42:08 PM PDT 24
Peak memory 195752 kb
Host smart-3f7b3cf6-279e-42c9-b25f-089d4328fb96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306459418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.3306459418
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.3449257579
Short name T166
Test name
Test status
Simulation time 82725459 ps
CPU time 1.3 seconds
Started May 23 12:42:06 PM PDT 24
Finished May 23 12:42:09 PM PDT 24
Peak memory 196664 kb
Host smart-a110fab2-a7ae-4a5f-b438-98c00b972bbf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449257579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.3449257579
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.1230039749
Short name T14
Test name
Test status
Simulation time 51786911 ps
CPU time 1.47 seconds
Started May 23 12:42:05 PM PDT 24
Finished May 23 12:42:08 PM PDT 24
Peak memory 196624 kb
Host smart-9b595383-810e-4d6e-9e22-5adbfef79515
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230039749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.1230039749
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.3076658123
Short name T585
Test name
Test status
Simulation time 65639862 ps
CPU time 1.42 seconds
Started May 23 12:42:06 PM PDT 24
Finished May 23 12:42:09 PM PDT 24
Peak memory 195968 kb
Host smart-01324ac5-8f15-4089-87ce-12dbe457e0e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076658123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
3076658123
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.2535835554
Short name T462
Test name
Test status
Simulation time 18501507 ps
CPU time 0.81 seconds
Started May 23 12:42:02 PM PDT 24
Finished May 23 12:42:04 PM PDT 24
Peak memory 197164 kb
Host smart-e09c6d9f-958e-4407-990f-ebbd54b3d254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535835554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.2535835554
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.1645303864
Short name T157
Test name
Test status
Simulation time 75216735 ps
CPU time 0.8 seconds
Started May 23 12:42:03 PM PDT 24
Finished May 23 12:42:05 PM PDT 24
Peak memory 196544 kb
Host smart-151a9480-842b-4d81-9560-e3b610e7ed37
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645303864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.1645303864
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.500407439
Short name T298
Test name
Test status
Simulation time 335913322 ps
CPU time 2.15 seconds
Started May 23 12:42:03 PM PDT 24
Finished May 23 12:42:06 PM PDT 24
Peak memory 197700 kb
Host smart-33aea6cc-e021-4877-85cc-546a0393407f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500407439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand
om_long_reg_writes_reg_reads.500407439
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.1378341063
Short name T629
Test name
Test status
Simulation time 66628196 ps
CPU time 1.1 seconds
Started May 23 12:42:01 PM PDT 24
Finished May 23 12:42:03 PM PDT 24
Peak memory 195648 kb
Host smart-546ae96b-7352-4d4d-ba47-0b34b376ebe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378341063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.1378341063
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.916751062
Short name T124
Test name
Test status
Simulation time 38030182 ps
CPU time 0.8 seconds
Started May 23 12:42:04 PM PDT 24
Finished May 23 12:42:07 PM PDT 24
Peak memory 195096 kb
Host smart-9e575e85-2545-49df-9e1c-99b91c078466
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916751062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.916751062
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.2513214184
Short name T347
Test name
Test status
Simulation time 21366564857 ps
CPU time 225.08 seconds
Started May 23 12:42:08 PM PDT 24
Finished May 23 12:45:54 PM PDT 24
Peak memory 198016 kb
Host smart-682f51b5-e64e-4116-8571-0f9522f33500
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513214184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.2513214184
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.2476765384
Short name T69
Test name
Test status
Simulation time 146445059353 ps
CPU time 1676.51 seconds
Started May 23 12:42:00 PM PDT 24
Finished May 23 01:09:58 PM PDT 24
Peak memory 198096 kb
Host smart-bd9732be-de95-4b2e-8592-a81c107f7a9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2476765384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.2476765384
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.690707366
Short name T633
Test name
Test status
Simulation time 21514562 ps
CPU time 0.62 seconds
Started May 23 12:42:06 PM PDT 24
Finished May 23 12:42:08 PM PDT 24
Peak memory 193764 kb
Host smart-f3368ddd-282f-49c2-909c-a65bff88e845
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690707366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.690707366
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.909501576
Short name T197
Test name
Test status
Simulation time 39717080 ps
CPU time 0.85 seconds
Started May 23 12:42:03 PM PDT 24
Finished May 23 12:42:05 PM PDT 24
Peak memory 196440 kb
Host smart-fe93aa54-a413-4e97-937f-8d61d085c23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909501576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.909501576
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.3664975733
Short name T560
Test name
Test status
Simulation time 152148831 ps
CPU time 4.67 seconds
Started May 23 12:42:06 PM PDT 24
Finished May 23 12:42:12 PM PDT 24
Peak memory 195844 kb
Host smart-59b3afd2-6dd8-4852-ac62-d4088a613825
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664975733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.3664975733
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.2202809980
Short name T131
Test name
Test status
Simulation time 80988156 ps
CPU time 1.15 seconds
Started May 23 12:42:05 PM PDT 24
Finished May 23 12:42:07 PM PDT 24
Peak memory 197720 kb
Host smart-ce8f6218-8789-49c5-b0fd-5263e27930c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202809980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.2202809980
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.1612760600
Short name T688
Test name
Test status
Simulation time 52912466 ps
CPU time 0.95 seconds
Started May 23 12:42:04 PM PDT 24
Finished May 23 12:42:07 PM PDT 24
Peak memory 196636 kb
Host smart-791b8392-2da2-42a3-a56e-ce72c9654df7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612760600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.1612760600
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.1373186064
Short name T163
Test name
Test status
Simulation time 388780539 ps
CPU time 3.35 seconds
Started May 23 12:42:03 PM PDT 24
Finished May 23 12:42:08 PM PDT 24
Peak memory 197684 kb
Host smart-1feeabb3-7af4-47ce-a173-93f765008223
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373186064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.1373186064
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.2201810121
Short name T274
Test name
Test status
Simulation time 136845615 ps
CPU time 2.59 seconds
Started May 23 12:42:03 PM PDT 24
Finished May 23 12:42:08 PM PDT 24
Peak memory 196880 kb
Host smart-2a71e024-2d32-4a93-9b15-2b4f37bd6146
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201810121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
2201810121
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.1758917884
Short name T390
Test name
Test status
Simulation time 37953956 ps
CPU time 0.91 seconds
Started May 23 12:42:03 PM PDT 24
Finished May 23 12:42:05 PM PDT 24
Peak memory 196448 kb
Host smart-31fbdcde-5942-49f9-9bb6-ee3d8b0b6fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758917884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.1758917884
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.2035174294
Short name T520
Test name
Test status
Simulation time 49184167 ps
CPU time 0.74 seconds
Started May 23 12:42:06 PM PDT 24
Finished May 23 12:42:08 PM PDT 24
Peak memory 195252 kb
Host smart-0e48e69a-1e1c-4174-9677-09f62536e762
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035174294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.2035174294
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.3952818902
Short name T139
Test name
Test status
Simulation time 197272914 ps
CPU time 3.2 seconds
Started May 23 12:42:03 PM PDT 24
Finished May 23 12:42:07 PM PDT 24
Peak memory 197748 kb
Host smart-a8621cc3-ad28-44df-9718-d682293034cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952818902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.3952818902
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.2254628597
Short name T219
Test name
Test status
Simulation time 684573687 ps
CPU time 1.24 seconds
Started May 23 12:42:05 PM PDT 24
Finished May 23 12:42:08 PM PDT 24
Peak memory 197912 kb
Host smart-17d36fcf-3fa2-4a22-8eda-fe9139a250a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254628597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.2254628597
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.473027070
Short name T244
Test name
Test status
Simulation time 97580198 ps
CPU time 1.32 seconds
Started May 23 12:42:04 PM PDT 24
Finished May 23 12:42:07 PM PDT 24
Peak memory 195652 kb
Host smart-654b28c6-71f1-462f-afc3-db17f52d197e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473027070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.473027070
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.1937531994
Short name T152
Test name
Test status
Simulation time 13270835232 ps
CPU time 151.31 seconds
Started May 23 12:42:06 PM PDT 24
Finished May 23 12:44:39 PM PDT 24
Peak memory 198100 kb
Host smart-f3653a79-7d12-4a64-9447-36b15e01edda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937531994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.1937531994
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.4226990140
Short name T546
Test name
Test status
Simulation time 21322230 ps
CPU time 0.63 seconds
Started May 23 12:42:04 PM PDT 24
Finished May 23 12:42:07 PM PDT 24
Peak memory 194528 kb
Host smart-c648bdcc-468f-4b51-a9b2-cf054231fbb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226990140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.4226990140
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.444080113
Short name T545
Test name
Test status
Simulation time 150520349 ps
CPU time 0.91 seconds
Started May 23 12:42:03 PM PDT 24
Finished May 23 12:42:06 PM PDT 24
Peak memory 195764 kb
Host smart-06b10bcc-4234-4acb-9a9d-f82d1dde55c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444080113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.444080113
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.4013381673
Short name T663
Test name
Test status
Simulation time 2203484176 ps
CPU time 18.49 seconds
Started May 23 12:42:04 PM PDT 24
Finished May 23 12:42:24 PM PDT 24
Peak memory 197944 kb
Host smart-3c0e0db0-02aa-44ca-aa4a-95e016d2c752
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013381673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.4013381673
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.928658843
Short name T661
Test name
Test status
Simulation time 68966683 ps
CPU time 0.98 seconds
Started May 23 12:42:03 PM PDT 24
Finished May 23 12:42:06 PM PDT 24
Peak memory 197552 kb
Host smart-568338dd-1e95-46b5-b5c1-73eea050c585
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928658843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.928658843
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.483189605
Short name T394
Test name
Test status
Simulation time 54975135 ps
CPU time 1.41 seconds
Started May 23 12:42:08 PM PDT 24
Finished May 23 12:42:10 PM PDT 24
Peak memory 195624 kb
Host smart-d9eb42a4-27df-4e71-a31b-3b6eebdd22d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483189605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.483189605
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.2900629464
Short name T696
Test name
Test status
Simulation time 279198639 ps
CPU time 3.29 seconds
Started May 23 12:42:04 PM PDT 24
Finished May 23 12:42:10 PM PDT 24
Peak memory 197748 kb
Host smart-afd214b6-286e-4d76-84aa-4909ee903d05
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900629464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.2900629464
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.1101904490
Short name T711
Test name
Test status
Simulation time 51725555 ps
CPU time 1.43 seconds
Started May 23 12:42:02 PM PDT 24
Finished May 23 12:42:05 PM PDT 24
Peak memory 196692 kb
Host smart-17fdeb7e-7b4f-48b1-bf56-11d6e9c1e219
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101904490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
1101904490
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.1174253132
Short name T169
Test name
Test status
Simulation time 39947818 ps
CPU time 0.65 seconds
Started May 23 12:42:04 PM PDT 24
Finished May 23 12:42:07 PM PDT 24
Peak memory 194184 kb
Host smart-94bb06e1-aa63-4d0a-8b15-72b961752314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174253132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.1174253132
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.3376564429
Short name T13
Test name
Test status
Simulation time 162214773 ps
CPU time 1.14 seconds
Started May 23 12:42:01 PM PDT 24
Finished May 23 12:42:04 PM PDT 24
Peak memory 195932 kb
Host smart-4d93e9b7-046c-424f-846c-3105526db149
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376564429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.3376564429
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.3038664160
Short name T599
Test name
Test status
Simulation time 152326593 ps
CPU time 1.81 seconds
Started May 23 12:42:05 PM PDT 24
Finished May 23 12:42:08 PM PDT 24
Peak memory 197732 kb
Host smart-75b1b326-de4b-448a-9363-fa7146abdac0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038664160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.3038664160
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.2671976633
Short name T365
Test name
Test status
Simulation time 41869766 ps
CPU time 0.79 seconds
Started May 23 12:42:04 PM PDT 24
Finished May 23 12:42:10 PM PDT 24
Peak memory 195120 kb
Host smart-755cd8d4-e175-41fd-9f64-abd95d2a8553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671976633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.2671976633
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.3585844300
Short name T584
Test name
Test status
Simulation time 88148670 ps
CPU time 1.35 seconds
Started May 23 12:42:06 PM PDT 24
Finished May 23 12:42:09 PM PDT 24
Peak memory 196776 kb
Host smart-10dc9d81-55bb-492a-92b3-82084cf7fdeb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585844300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.3585844300
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.128884170
Short name T682
Test name
Test status
Simulation time 47941885323 ps
CPU time 80.29 seconds
Started May 23 12:42:03 PM PDT 24
Finished May 23 12:43:25 PM PDT 24
Peak memory 198144 kb
Host smart-b41e9d2f-3633-44d8-8750-97d9b08282b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128884170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gp
io_stress_all.128884170
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.2836249065
Short name T472
Test name
Test status
Simulation time 22712993 ps
CPU time 0.56 seconds
Started May 23 12:42:17 PM PDT 24
Finished May 23 12:42:18 PM PDT 24
Peak memory 193740 kb
Host smart-2b07777f-3aa2-4fc7-8d36-ff3b78f46f53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836249065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.2836249065
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.51188693
Short name T136
Test name
Test status
Simulation time 204167775 ps
CPU time 1.01 seconds
Started May 23 12:42:07 PM PDT 24
Finished May 23 12:42:09 PM PDT 24
Peak memory 195872 kb
Host smart-67d4f7c3-25e6-4835-8340-0abf3df8c173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51188693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.51188693
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.2287570548
Short name T336
Test name
Test status
Simulation time 1012663753 ps
CPU time 13.43 seconds
Started May 23 12:42:19 PM PDT 24
Finished May 23 12:42:34 PM PDT 24
Peak memory 196748 kb
Host smart-4f615b84-24d6-4144-857a-62f23f7fa759
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287570548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.2287570548
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.2282861527
Short name T258
Test name
Test status
Simulation time 46237707 ps
CPU time 0.83 seconds
Started May 23 12:42:22 PM PDT 24
Finished May 23 12:42:25 PM PDT 24
Peak memory 195864 kb
Host smart-7611f936-74ac-4ed1-9ee8-7aa4598dbe60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282861527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.2282861527
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.785572640
Short name T581
Test name
Test status
Simulation time 170988707 ps
CPU time 1.09 seconds
Started May 23 12:42:08 PM PDT 24
Finished May 23 12:42:10 PM PDT 24
Peak memory 195600 kb
Host smart-cea720e0-c887-462b-ad6c-b105320572dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785572640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.785572640
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.1800418698
Short name T12
Test name
Test status
Simulation time 79301164 ps
CPU time 0.98 seconds
Started May 23 12:42:17 PM PDT 24
Finished May 23 12:42:19 PM PDT 24
Peak memory 196892 kb
Host smart-d29496ee-3ef5-4fc0-b444-def1c2fd7f81
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800418698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.1800418698
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.1671838460
Short name T407
Test name
Test status
Simulation time 111595110 ps
CPU time 3.42 seconds
Started May 23 12:42:08 PM PDT 24
Finished May 23 12:42:13 PM PDT 24
Peak memory 197872 kb
Host smart-53f5bc12-c7c6-4ca8-8f8d-667b92fe9e35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671838460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
1671838460
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.4077205261
Short name T112
Test name
Test status
Simulation time 55355432 ps
CPU time 1.06 seconds
Started May 23 12:42:03 PM PDT 24
Finished May 23 12:42:05 PM PDT 24
Peak memory 195824 kb
Host smart-8e4ade63-8ebe-42ea-acb6-52f238f1cb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077205261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.4077205261
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.2914365417
Short name T170
Test name
Test status
Simulation time 92361042 ps
CPU time 1.71 seconds
Started May 23 12:42:16 PM PDT 24
Finished May 23 12:42:19 PM PDT 24
Peak memory 197732 kb
Host smart-e6416fd9-a7b5-46ae-a460-7f34be95620e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914365417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.2914365417
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.1574001348
Short name T125
Test name
Test status
Simulation time 64027985 ps
CPU time 1.13 seconds
Started May 23 12:42:05 PM PDT 24
Finished May 23 12:42:08 PM PDT 24
Peak memory 195456 kb
Host smart-387e0a9f-dd0b-422c-93eb-29a34b25fb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574001348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.1574001348
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.216214449
Short name T616
Test name
Test status
Simulation time 35927458 ps
CPU time 1.14 seconds
Started May 23 12:42:03 PM PDT 24
Finished May 23 12:42:06 PM PDT 24
Peak memory 196348 kb
Host smart-d001ae70-af55-4f10-a81d-26b168097335
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216214449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.216214449
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.2362603203
Short name T447
Test name
Test status
Simulation time 66963416730 ps
CPU time 187.24 seconds
Started May 23 12:42:20 PM PDT 24
Finished May 23 12:45:29 PM PDT 24
Peak memory 198056 kb
Host smart-812c5103-97e4-414c-8df6-d6b7641a4fd2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362603203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.2362603203
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.2251853472
Short name T561
Test name
Test status
Simulation time 46052636325 ps
CPU time 579.27 seconds
Started May 23 12:42:20 PM PDT 24
Finished May 23 12:52:01 PM PDT 24
Peak memory 198148 kb
Host smart-f21c1848-1811-48cb-8f26-7ae302d539b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2251853472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.2251853472
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.2365337554
Short name T385
Test name
Test status
Simulation time 51645811 ps
CPU time 0.62 seconds
Started May 23 12:42:16 PM PDT 24
Finished May 23 12:42:17 PM PDT 24
Peak memory 193884 kb
Host smart-868d9488-9f6e-440d-a2e4-7a8fd94f4674
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365337554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.2365337554
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.1235836359
Short name T18
Test name
Test status
Simulation time 14638084 ps
CPU time 0.64 seconds
Started May 23 12:42:19 PM PDT 24
Finished May 23 12:42:21 PM PDT 24
Peak memory 194020 kb
Host smart-2ae98f04-8c35-49b3-af8a-12f94f42957a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235836359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.1235836359
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.983767261
Short name T685
Test name
Test status
Simulation time 147333088 ps
CPU time 8.27 seconds
Started May 23 12:42:22 PM PDT 24
Finished May 23 12:42:33 PM PDT 24
Peak memory 197824 kb
Host smart-87785351-873b-460c-8890-e134c126435a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983767261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stress
.983767261
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.3001131408
Short name T574
Test name
Test status
Simulation time 80122121 ps
CPU time 0.75 seconds
Started May 23 12:42:22 PM PDT 24
Finished May 23 12:42:24 PM PDT 24
Peak memory 195804 kb
Host smart-fca7fb6c-bf0b-43e3-b74b-17fb2c9cd639
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001131408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.3001131408
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.141976214
Short name T315
Test name
Test status
Simulation time 117570329 ps
CPU time 0.8 seconds
Started May 23 12:42:16 PM PDT 24
Finished May 23 12:42:17 PM PDT 24
Peak memory 195352 kb
Host smart-e052cbcd-b9eb-46e8-8ef4-75ba40474367
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141976214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.141976214
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.1782979629
Short name T346
Test name
Test status
Simulation time 84854433 ps
CPU time 3.09 seconds
Started May 23 12:42:24 PM PDT 24
Finished May 23 12:42:30 PM PDT 24
Peak memory 197980 kb
Host smart-dd73e1ff-ee40-4dbd-8d2e-a737f28b41e3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782979629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.1782979629
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.1385052488
Short name T550
Test name
Test status
Simulation time 412414957 ps
CPU time 2.18 seconds
Started May 23 12:42:23 PM PDT 24
Finished May 23 12:42:29 PM PDT 24
Peak memory 195920 kb
Host smart-f7f1ffb8-6ce7-4941-9af3-5865a32a3ae1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385052488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
1385052488
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.2434009769
Short name T664
Test name
Test status
Simulation time 46478122 ps
CPU time 0.98 seconds
Started May 23 12:42:22 PM PDT 24
Finished May 23 12:42:25 PM PDT 24
Peak memory 195696 kb
Host smart-6ed5203b-02ca-4fc6-bcb1-8d79eeb4a07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434009769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.2434009769
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.2595843790
Short name T262
Test name
Test status
Simulation time 39001098 ps
CPU time 1.25 seconds
Started May 23 12:42:14 PM PDT 24
Finished May 23 12:42:15 PM PDT 24
Peak memory 198036 kb
Host smart-139e3eb1-a686-4f62-b9d5-90baffd0c553
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595843790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.2595843790
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.1875032649
Short name T254
Test name
Test status
Simulation time 526531814 ps
CPU time 2.17 seconds
Started May 23 12:42:18 PM PDT 24
Finished May 23 12:42:21 PM PDT 24
Peak memory 197848 kb
Host smart-d92f4981-0790-4d92-86cc-781770b07ef6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875032649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.1875032649
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.2191260821
Short name T235
Test name
Test status
Simulation time 249595849 ps
CPU time 0.88 seconds
Started May 23 12:42:15 PM PDT 24
Finished May 23 12:42:16 PM PDT 24
Peak memory 195412 kb
Host smart-8d081cd6-03b6-436c-a66b-c9bcb9e770b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191260821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.2191260821
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.247217739
Short name T256
Test name
Test status
Simulation time 90512000 ps
CPU time 1 seconds
Started May 23 12:42:22 PM PDT 24
Finished May 23 12:42:26 PM PDT 24
Peak memory 195536 kb
Host smart-f2f31776-a5f6-4005-9069-18eb1408007f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247217739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.247217739
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.3677656355
Short name T499
Test name
Test status
Simulation time 2403874413 ps
CPU time 26.6 seconds
Started May 23 12:42:15 PM PDT 24
Finished May 23 12:42:42 PM PDT 24
Peak memory 198032 kb
Host smart-60a6ee8a-7ed8-4fc9-98b7-9b83673ee0ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677656355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.3677656355
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.3190212193
Short name T37
Test name
Test status
Simulation time 33686154460 ps
CPU time 920.53 seconds
Started May 23 12:42:22 PM PDT 24
Finished May 23 12:57:45 PM PDT 24
Peak memory 197920 kb
Host smart-b7e2e7ff-74ae-4324-b51a-3e5c4df823ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3190212193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.3190212193
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3172795381
Short name T919
Test name
Test status
Simulation time 271669041 ps
CPU time 1.13 seconds
Started May 23 12:41:15 PM PDT 24
Finished May 23 12:41:18 PM PDT 24
Peak memory 197820 kb
Host smart-47968aae-5e18-4cc8-9ece-925cfefff84a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3172795381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.3172795381
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3794427198
Short name T842
Test name
Test status
Simulation time 117790892 ps
CPU time 1.1 seconds
Started May 23 12:41:16 PM PDT 24
Finished May 23 12:41:19 PM PDT 24
Peak memory 192136 kb
Host smart-759c1e6d-7985-4ffb-b498-358370993d9e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794427198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3794427198
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.2606037808
Short name T893
Test name
Test status
Simulation time 35497825 ps
CPU time 1.12 seconds
Started May 23 12:41:15 PM PDT 24
Finished May 23 12:41:18 PM PDT 24
Peak memory 192092 kb
Host smart-2efdb604-cf55-4f57-9263-007ed7227d02
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2606037808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.2606037808
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.644772374
Short name T870
Test name
Test status
Simulation time 192254086 ps
CPU time 1.41 seconds
Started May 23 12:41:11 PM PDT 24
Finished May 23 12:41:14 PM PDT 24
Peak memory 192172 kb
Host smart-16ed7360-55f4-41ba-91c5-0db378cd408b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644772374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.644772374
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3180608822
Short name T868
Test name
Test status
Simulation time 98617783 ps
CPU time 0.83 seconds
Started May 23 12:41:22 PM PDT 24
Finished May 23 12:41:24 PM PDT 24
Peak memory 191892 kb
Host smart-35d3493d-b00e-4bf0-b5e5-a544db8c8a6f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3180608822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.3180608822
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3334210183
Short name T886
Test name
Test status
Simulation time 90318104 ps
CPU time 1.6 seconds
Started May 23 12:41:25 PM PDT 24
Finished May 23 12:41:29 PM PDT 24
Peak memory 198600 kb
Host smart-f462ed3d-beff-4a03-a2ab-18d443fe1c74
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334210183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3334210183
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.4063610129
Short name T873
Test name
Test status
Simulation time 363664803 ps
CPU time 1.25 seconds
Started May 23 12:41:24 PM PDT 24
Finished May 23 12:41:28 PM PDT 24
Peak memory 192220 kb
Host smart-f7410989-8543-4e3a-9cde-29b3d4f17407
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4063610129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.4063610129
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.55626552
Short name T910
Test name
Test status
Simulation time 80490535 ps
CPU time 1.37 seconds
Started May 23 12:41:23 PM PDT 24
Finished May 23 12:41:26 PM PDT 24
Peak memory 198500 kb
Host smart-c54558c8-8f0f-4450-98b8-d78f922bcf5c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55626552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.55626552
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2148815308
Short name T903
Test name
Test status
Simulation time 91691231 ps
CPU time 1.04 seconds
Started May 23 12:41:23 PM PDT 24
Finished May 23 12:41:26 PM PDT 24
Peak memory 192132 kb
Host smart-b122ce8b-7de5-4952-a968-bbcdd716f906
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2148815308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.2148815308
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2433609954
Short name T918
Test name
Test status
Simulation time 199910533 ps
CPU time 1.12 seconds
Started May 23 12:41:25 PM PDT 24
Finished May 23 12:41:28 PM PDT 24
Peak memory 198292 kb
Host smart-4c035f63-5ce7-4b80-b0bd-306e913a1ab8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433609954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2433609954
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.363571659
Short name T917
Test name
Test status
Simulation time 46545563 ps
CPU time 1.02 seconds
Started May 23 12:41:24 PM PDT 24
Finished May 23 12:41:28 PM PDT 24
Peak memory 192116 kb
Host smart-354adec2-d442-4f81-8e11-5d3c9fb1330b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=363571659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.363571659
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1336278138
Short name T900
Test name
Test status
Simulation time 49653191 ps
CPU time 1.06 seconds
Started May 23 12:41:22 PM PDT 24
Finished May 23 12:41:24 PM PDT 24
Peak memory 192036 kb
Host smart-e2d4e58e-fcd9-4e6f-a637-86e7ae12ce8f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336278138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1336278138
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2273241579
Short name T875
Test name
Test status
Simulation time 54830868 ps
CPU time 0.72 seconds
Started May 23 12:41:22 PM PDT 24
Finished May 23 12:41:25 PM PDT 24
Peak memory 192140 kb
Host smart-e9bc1895-fdce-499b-b315-33d58aec49e5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2273241579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.2273241579
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.718911296
Short name T922
Test name
Test status
Simulation time 61800517 ps
CPU time 1.1 seconds
Started May 23 12:41:25 PM PDT 24
Finished May 23 12:41:28 PM PDT 24
Peak memory 196816 kb
Host smart-bbadd796-2c69-4d67-b266-f771137c7004
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718911296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.718911296
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1082668048
Short name T841
Test name
Test status
Simulation time 1500793522 ps
CPU time 1.29 seconds
Started May 23 12:41:24 PM PDT 24
Finished May 23 12:41:27 PM PDT 24
Peak memory 192088 kb
Host smart-49a0f186-49cb-41cf-8ebd-318035478413
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1082668048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.1082668048
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4129455280
Short name T925
Test name
Test status
Simulation time 147472112 ps
CPU time 1.32 seconds
Started May 23 12:41:24 PM PDT 24
Finished May 23 12:41:28 PM PDT 24
Peak memory 192140 kb
Host smart-a9e37613-22e5-4d66-9bef-d7d122c6157c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129455280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4129455280
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1572560312
Short name T849
Test name
Test status
Simulation time 70973499 ps
CPU time 1 seconds
Started May 23 12:41:28 PM PDT 24
Finished May 23 12:41:31 PM PDT 24
Peak memory 198400 kb
Host smart-fb465e9c-5a8b-425a-9f0f-66ef505e02f4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1572560312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.1572560312
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2805362345
Short name T852
Test name
Test status
Simulation time 182666734 ps
CPU time 0.74 seconds
Started May 23 12:41:24 PM PDT 24
Finished May 23 12:41:27 PM PDT 24
Peak memory 196588 kb
Host smart-55f3861b-f8dd-4a27-8039-ada04214aaf3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805362345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2805362345
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.916980803
Short name T887
Test name
Test status
Simulation time 193931773 ps
CPU time 1.06 seconds
Started May 23 12:41:29 PM PDT 24
Finished May 23 12:41:32 PM PDT 24
Peak memory 196920 kb
Host smart-3d340a39-5d11-438a-8060-3bea1f74b047
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=916980803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.916980803
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3288703917
Short name T864
Test name
Test status
Simulation time 46079493 ps
CPU time 1.35 seconds
Started May 23 12:41:26 PM PDT 24
Finished May 23 12:41:30 PM PDT 24
Peak memory 192180 kb
Host smart-f4b15cdd-decf-42ca-a1c0-cd0858e194da
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288703917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3288703917
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3061386461
Short name T933
Test name
Test status
Simulation time 159898646 ps
CPU time 1.32 seconds
Started May 23 12:41:26 PM PDT 24
Finished May 23 12:41:30 PM PDT 24
Peak memory 198428 kb
Host smart-619153a6-acae-435c-8bda-5c8ae931fd4c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3061386461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.3061386461
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1440357998
Short name T929
Test name
Test status
Simulation time 66376284 ps
CPU time 1.15 seconds
Started May 23 12:41:28 PM PDT 24
Finished May 23 12:41:31 PM PDT 24
Peak memory 192132 kb
Host smart-66500bf0-7eb5-4ee5-9680-2ea4b77241ec
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440357998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1440357998
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3979890148
Short name T904
Test name
Test status
Simulation time 59119811 ps
CPU time 1.12 seconds
Started May 23 12:41:23 PM PDT 24
Finished May 23 12:41:25 PM PDT 24
Peak memory 192096 kb
Host smart-d796ca7c-0ba1-449f-ae20-0ee59da1c19c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3979890148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.3979890148
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1880189960
Short name T932
Test name
Test status
Simulation time 120183246 ps
CPU time 1.25 seconds
Started May 23 12:41:25 PM PDT 24
Finished May 23 12:41:29 PM PDT 24
Peak memory 192256 kb
Host smart-9dd2c5de-3959-45c4-a2c0-9d32c3908146
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880189960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1880189960
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.169915108
Short name T914
Test name
Test status
Simulation time 403814730 ps
CPU time 1.23 seconds
Started May 23 12:41:14 PM PDT 24
Finished May 23 12:41:18 PM PDT 24
Peak memory 192128 kb
Host smart-7fd9f4c7-7029-4ae7-838a-ad4fe0e7fa42
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=169915108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.169915108
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3688065726
Short name T940
Test name
Test status
Simulation time 117250461 ps
CPU time 1.21 seconds
Started May 23 12:41:28 PM PDT 24
Finished May 23 12:41:31 PM PDT 24
Peak memory 192124 kb
Host smart-401c4bab-d5bb-40ad-8b5f-9d6498c64076
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688065726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3688065726
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.4017215332
Short name T874
Test name
Test status
Simulation time 180338641 ps
CPU time 0.82 seconds
Started May 23 12:41:28 PM PDT 24
Finished May 23 12:41:31 PM PDT 24
Peak memory 191940 kb
Host smart-a7b1ff99-046b-488b-af36-9f98fb465e51
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4017215332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.4017215332
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3407957745
Short name T859
Test name
Test status
Simulation time 114759325 ps
CPU time 1.52 seconds
Started May 23 12:41:27 PM PDT 24
Finished May 23 12:41:31 PM PDT 24
Peak memory 192152 kb
Host smart-18068770-93e2-4b26-a86b-058143adb021
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407957745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3407957745
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2817464764
Short name T843
Test name
Test status
Simulation time 49027972 ps
CPU time 1.07 seconds
Started May 23 12:41:29 PM PDT 24
Finished May 23 12:41:32 PM PDT 24
Peak memory 192100 kb
Host smart-f58a7fc3-165e-4646-a27e-fa1457d73ec5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2817464764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.2817464764
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2003665187
Short name T883
Test name
Test status
Simulation time 469570651 ps
CPU time 1.42 seconds
Started May 23 12:41:24 PM PDT 24
Finished May 23 12:41:27 PM PDT 24
Peak memory 192100 kb
Host smart-1aa81925-52ad-422d-b3a1-c3f4d9ec60f4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003665187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2003665187
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3622701057
Short name T871
Test name
Test status
Simulation time 225147447 ps
CPU time 0.84 seconds
Started May 23 12:41:24 PM PDT 24
Finished May 23 12:41:26 PM PDT 24
Peak memory 191884 kb
Host smart-5b7b58fb-1949-4c8c-a249-9a2233c53332
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3622701057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.3622701057
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3189730815
Short name T896
Test name
Test status
Simulation time 161948916 ps
CPU time 1.14 seconds
Started May 23 12:41:23 PM PDT 24
Finished May 23 12:41:26 PM PDT 24
Peak memory 192144 kb
Host smart-597b1ac2-b301-41ae-9d15-7f861db89668
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189730815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3189730815
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1567523804
Short name T853
Test name
Test status
Simulation time 258075556 ps
CPU time 1.15 seconds
Started May 23 12:41:26 PM PDT 24
Finished May 23 12:41:30 PM PDT 24
Peak memory 192244 kb
Host smart-67f32795-2b44-42c1-b21d-6ae6e9abe14b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1567523804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.1567523804
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1538141698
Short name T857
Test name
Test status
Simulation time 197396525 ps
CPU time 1.02 seconds
Started May 23 12:41:25 PM PDT 24
Finished May 23 12:41:29 PM PDT 24
Peak memory 198464 kb
Host smart-f30f2979-4b9b-439f-85c0-a73bbed4a8c8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538141698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1538141698
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.390559678
Short name T891
Test name
Test status
Simulation time 51904031 ps
CPU time 1.04 seconds
Started May 23 12:41:29 PM PDT 24
Finished May 23 12:41:32 PM PDT 24
Peak memory 198456 kb
Host smart-6479a30a-e554-4783-86fb-22a1b4942f85
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=390559678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.390559678
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1372952951
Short name T902
Test name
Test status
Simulation time 28849608 ps
CPU time 0.92 seconds
Started May 23 12:41:25 PM PDT 24
Finished May 23 12:41:29 PM PDT 24
Peak memory 192156 kb
Host smart-e4990891-110f-4795-9649-b6dff7decd69
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372952951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1372952951
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3386843982
Short name T926
Test name
Test status
Simulation time 96270200 ps
CPU time 0.8 seconds
Started May 23 12:41:28 PM PDT 24
Finished May 23 12:41:31 PM PDT 24
Peak memory 191800 kb
Host smart-c3335a33-3c9f-4996-9539-4a786e6adc74
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3386843982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.3386843982
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3853765110
Short name T856
Test name
Test status
Simulation time 219086814 ps
CPU time 1.15 seconds
Started May 23 12:41:28 PM PDT 24
Finished May 23 12:41:32 PM PDT 24
Peak memory 192088 kb
Host smart-5041b622-8485-4bba-801b-c2f5d8e79355
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853765110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3853765110
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1033502057
Short name T912
Test name
Test status
Simulation time 87700908 ps
CPU time 0.93 seconds
Started May 23 12:41:29 PM PDT 24
Finished May 23 12:41:32 PM PDT 24
Peak memory 192040 kb
Host smart-f7f621ba-f133-4269-a545-f0dc8af7fefd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1033502057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.1033502057
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2743991871
Short name T913
Test name
Test status
Simulation time 33715527 ps
CPU time 1.06 seconds
Started May 23 12:41:25 PM PDT 24
Finished May 23 12:41:28 PM PDT 24
Peak memory 192140 kb
Host smart-82e09c30-9ecd-4134-9a87-f13d2b54059a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743991871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2743991871
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.287338795
Short name T916
Test name
Test status
Simulation time 40603143 ps
CPU time 0.88 seconds
Started May 23 12:41:26 PM PDT 24
Finished May 23 12:41:29 PM PDT 24
Peak memory 191904 kb
Host smart-6c1277dd-657d-4116-ba33-afd724d827aa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=287338795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.287338795
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.459491898
Short name T937
Test name
Test status
Simulation time 166154329 ps
CPU time 1 seconds
Started May 23 12:41:30 PM PDT 24
Finished May 23 12:41:32 PM PDT 24
Peak memory 192192 kb
Host smart-ba8c5827-64bc-43ea-b703-9cb87ff127be
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459491898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.459491898
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.572295271
Short name T921
Test name
Test status
Simulation time 48918426 ps
CPU time 1.37 seconds
Started May 23 12:41:30 PM PDT 24
Finished May 23 12:41:33 PM PDT 24
Peak memory 198516 kb
Host smart-abaf7d1f-d0c6-4837-8efb-11a854595664
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=572295271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.572295271
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2384965081
Short name T878
Test name
Test status
Simulation time 479790064 ps
CPU time 1.41 seconds
Started May 23 12:41:28 PM PDT 24
Finished May 23 12:41:31 PM PDT 24
Peak memory 198552 kb
Host smart-e1e7f9c2-296b-4366-89d2-c69dfe8296a7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384965081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2384965081
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3741276505
Short name T858
Test name
Test status
Simulation time 196974375 ps
CPU time 1.04 seconds
Started May 23 12:41:28 PM PDT 24
Finished May 23 12:41:31 PM PDT 24
Peak memory 192164 kb
Host smart-018e1573-0104-4739-b1a4-bed9c3017d88
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3741276505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.3741276505
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.652818692
Short name T850
Test name
Test status
Simulation time 33713571 ps
CPU time 0.94 seconds
Started May 23 12:41:30 PM PDT 24
Finished May 23 12:41:32 PM PDT 24
Peak memory 191992 kb
Host smart-323ef47a-a43a-46da-a63e-be2fe2dad2e9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652818692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.652818692
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.689887222
Short name T915
Test name
Test status
Simulation time 87026407 ps
CPU time 1.36 seconds
Started May 23 12:41:26 PM PDT 24
Finished May 23 12:41:30 PM PDT 24
Peak memory 198428 kb
Host smart-0d7fca97-7ee1-4633-b99e-a50f21d59b7d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=689887222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.689887222
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1243286344
Short name T882
Test name
Test status
Simulation time 662344475 ps
CPU time 1.37 seconds
Started May 23 12:41:24 PM PDT 24
Finished May 23 12:41:28 PM PDT 24
Peak memory 192108 kb
Host smart-94a4cfbd-4769-4f77-88e9-8049b45a3cd0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243286344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1243286344
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1595477055
Short name T846
Test name
Test status
Simulation time 121904448 ps
CPU time 1.26 seconds
Started May 23 12:41:30 PM PDT 24
Finished May 23 12:41:33 PM PDT 24
Peak memory 192172 kb
Host smart-f1d6e41b-3b1d-4a2e-98de-742761ceb8e9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1595477055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.1595477055
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3842832112
Short name T855
Test name
Test status
Simulation time 101614319 ps
CPU time 1.47 seconds
Started May 23 12:41:29 PM PDT 24
Finished May 23 12:41:32 PM PDT 24
Peak memory 192184 kb
Host smart-6df0cfc3-5b78-4cdc-acec-c488b84c16d9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842832112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3842832112
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2448993491
Short name T890
Test name
Test status
Simulation time 37361795 ps
CPU time 1.1 seconds
Started May 23 12:41:32 PM PDT 24
Finished May 23 12:41:35 PM PDT 24
Peak memory 196888 kb
Host smart-c47c2395-49be-422b-a19b-7c3e63c92da4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2448993491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.2448993491
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1088656049
Short name T920
Test name
Test status
Simulation time 159532423 ps
CPU time 1.18 seconds
Started May 23 12:41:32 PM PDT 24
Finished May 23 12:41:35 PM PDT 24
Peak memory 192204 kb
Host smart-ddf54d40-0384-48b1-a0a3-f9eb6d8dd280
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088656049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1088656049
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3312682173
Short name T895
Test name
Test status
Simulation time 35443761 ps
CPU time 0.98 seconds
Started May 23 12:41:33 PM PDT 24
Finished May 23 12:41:35 PM PDT 24
Peak memory 192020 kb
Host smart-a70eec15-10c8-4a30-aca5-1224f5d95b0f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3312682173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.3312682173
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3302196583
Short name T901
Test name
Test status
Simulation time 232148635 ps
CPU time 1.16 seconds
Started May 23 12:41:32 PM PDT 24
Finished May 23 12:41:35 PM PDT 24
Peak memory 192184 kb
Host smart-acd78d04-d7cc-4d8a-b9cc-7ea023875edf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302196583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3302196583
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.459489841
Short name T909
Test name
Test status
Simulation time 147094785 ps
CPU time 1.05 seconds
Started May 23 12:41:31 PM PDT 24
Finished May 23 12:41:34 PM PDT 24
Peak memory 192176 kb
Host smart-9bbc5044-a165-4d85-9b04-370b9ed630f2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=459489841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.459489841
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3424367395
Short name T861
Test name
Test status
Simulation time 127031467 ps
CPU time 1.23 seconds
Started May 23 12:41:23 PM PDT 24
Finished May 23 12:41:25 PM PDT 24
Peak memory 192140 kb
Host smart-0e30dd0c-d99a-43b0-8761-ab405d976ca1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424367395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3424367395
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.482526708
Short name T872
Test name
Test status
Simulation time 166592131 ps
CPU time 1.22 seconds
Started May 23 12:41:33 PM PDT 24
Finished May 23 12:41:35 PM PDT 24
Peak memory 192176 kb
Host smart-8931bc29-d8a5-4b8c-b479-cf63ee7158a8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=482526708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.482526708
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.816212033
Short name T888
Test name
Test status
Simulation time 62048858 ps
CPU time 1.1 seconds
Started May 23 12:41:26 PM PDT 24
Finished May 23 12:41:29 PM PDT 24
Peak memory 198056 kb
Host smart-175781e9-1a2d-418c-9fd6-e85e992329f2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816212033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.816212033
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2451665006
Short name T863
Test name
Test status
Simulation time 232550388 ps
CPU time 1.28 seconds
Started May 23 12:41:29 PM PDT 24
Finished May 23 12:41:32 PM PDT 24
Peak memory 192220 kb
Host smart-c9bbf4f4-8d03-4ed9-b41f-3799641d8788
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2451665006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.2451665006
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2425925941
Short name T877
Test name
Test status
Simulation time 245236110 ps
CPU time 1.07 seconds
Started May 23 12:41:38 PM PDT 24
Finished May 23 12:41:41 PM PDT 24
Peak memory 192156 kb
Host smart-67b33b36-4155-4543-837d-2484e43129ba
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425925941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2425925941
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3168919785
Short name T881
Test name
Test status
Simulation time 59968745 ps
CPU time 1 seconds
Started May 23 12:41:39 PM PDT 24
Finished May 23 12:41:42 PM PDT 24
Peak memory 192092 kb
Host smart-f6213861-61f2-436d-b05e-53f92e5ec671
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3168919785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.3168919785
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.494144840
Short name T862
Test name
Test status
Simulation time 36663996 ps
CPU time 1.07 seconds
Started May 23 12:41:37 PM PDT 24
Finished May 23 12:41:39 PM PDT 24
Peak memory 192064 kb
Host smart-8162f76f-c5ce-4fd6-b4c8-6a77961fc3fb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494144840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.494144840
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.4223378818
Short name T924
Test name
Test status
Simulation time 51885574 ps
CPU time 1.33 seconds
Started May 23 12:41:36 PM PDT 24
Finished May 23 12:41:39 PM PDT 24
Peak memory 196780 kb
Host smart-a20548cd-3e88-44aa-a23f-c82ea3bc397c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4223378818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.4223378818
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2697413284
Short name T894
Test name
Test status
Simulation time 467569915 ps
CPU time 1.03 seconds
Started May 23 12:41:37 PM PDT 24
Finished May 23 12:41:40 PM PDT 24
Peak memory 192184 kb
Host smart-0b9ec808-779f-43d1-9fef-9f774f215d44
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697413284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2697413284
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3363116013
Short name T851
Test name
Test status
Simulation time 129483041 ps
CPU time 0.99 seconds
Started May 23 12:41:37 PM PDT 24
Finished May 23 12:41:39 PM PDT 24
Peak memory 198164 kb
Host smart-21ff0fcb-edd5-4534-b08c-2f68d2f24a3e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3363116013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.3363116013
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1469792428
Short name T930
Test name
Test status
Simulation time 36373503 ps
CPU time 0.81 seconds
Started May 23 12:41:36 PM PDT 24
Finished May 23 12:41:38 PM PDT 24
Peak memory 191980 kb
Host smart-a12cbbb1-339b-4edc-8511-83bc255ed71e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469792428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1469792428
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3929994581
Short name T869
Test name
Test status
Simulation time 470936347 ps
CPU time 0.84 seconds
Started May 23 12:41:37 PM PDT 24
Finished May 23 12:41:39 PM PDT 24
Peak memory 191936 kb
Host smart-45ff447e-e4d8-46f8-adef-df609d809e7b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3929994581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.3929994581
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4179954810
Short name T911
Test name
Test status
Simulation time 160406571 ps
CPU time 1.35 seconds
Started May 23 12:41:38 PM PDT 24
Finished May 23 12:41:41 PM PDT 24
Peak memory 198496 kb
Host smart-6ba8324e-966d-4d15-8cf4-425d94526b25
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179954810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4179954810
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1294813566
Short name T906
Test name
Test status
Simulation time 36794526 ps
CPU time 0.86 seconds
Started May 23 12:41:22 PM PDT 24
Finished May 23 12:41:25 PM PDT 24
Peak memory 196760 kb
Host smart-5f42e32d-6676-4a91-a2e4-7d475e67f52e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1294813566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.1294813566
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.54927318
Short name T892
Test name
Test status
Simulation time 283464731 ps
CPU time 1.42 seconds
Started May 23 12:41:23 PM PDT 24
Finished May 23 12:41:26 PM PDT 24
Peak memory 192060 kb
Host smart-7d403795-a3d4-4ed4-a3a5-7fc64531e31c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54927318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.54927318
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.431823197
Short name T928
Test name
Test status
Simulation time 30892136 ps
CPU time 0.76 seconds
Started May 23 12:41:36 PM PDT 24
Finished May 23 12:41:38 PM PDT 24
Peak memory 192048 kb
Host smart-0d37806c-1df8-4b16-a4c7-79066fefa711
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=431823197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.431823197
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.638468218
Short name T927
Test name
Test status
Simulation time 37109463 ps
CPU time 1.05 seconds
Started May 23 12:41:43 PM PDT 24
Finished May 23 12:41:45 PM PDT 24
Peak memory 196888 kb
Host smart-bafa846c-b722-4134-9eb0-04f245bbb427
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638468218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.638468218
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1292698187
Short name T889
Test name
Test status
Simulation time 34958213 ps
CPU time 0.81 seconds
Started May 23 12:41:36 PM PDT 24
Finished May 23 12:41:37 PM PDT 24
Peak memory 191888 kb
Host smart-6d4788c9-d2cd-48e0-9fd7-5e775fd0bbf8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1292698187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.1292698187
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.857337783
Short name T854
Test name
Test status
Simulation time 130031621 ps
CPU time 1 seconds
Started May 23 12:41:37 PM PDT 24
Finished May 23 12:41:39 PM PDT 24
Peak memory 198456 kb
Host smart-701f275c-ae4d-4fbe-a8e8-802690aee70d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857337783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.857337783
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3685106993
Short name T905
Test name
Test status
Simulation time 40480685 ps
CPU time 1.11 seconds
Started May 23 12:41:37 PM PDT 24
Finished May 23 12:41:40 PM PDT 24
Peak memory 192060 kb
Host smart-ef303fdd-4e6e-4d67-b8b2-79a0a94a0157
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3685106993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.3685106993
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1258485273
Short name T880
Test name
Test status
Simulation time 50986347 ps
CPU time 1.3 seconds
Started May 23 12:41:39 PM PDT 24
Finished May 23 12:41:42 PM PDT 24
Peak memory 192160 kb
Host smart-32db59de-b9ed-46bd-a694-41fb4edde8fa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258485273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1258485273
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.466116352
Short name T923
Test name
Test status
Simulation time 621083248 ps
CPU time 1.07 seconds
Started May 23 12:41:38 PM PDT 24
Finished May 23 12:41:41 PM PDT 24
Peak memory 192080 kb
Host smart-f5637eec-aee2-45e1-bb84-7198c83ff789
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=466116352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.466116352
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1945126604
Short name T879
Test name
Test status
Simulation time 61851596 ps
CPU time 1.04 seconds
Started May 23 12:41:38 PM PDT 24
Finished May 23 12:41:41 PM PDT 24
Peak memory 192144 kb
Host smart-cde6417d-c4d5-4364-8654-4478db5e8e2d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945126604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1945126604
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.537420874
Short name T931
Test name
Test status
Simulation time 310194596 ps
CPU time 1.34 seconds
Started May 23 12:41:38 PM PDT 24
Finished May 23 12:41:42 PM PDT 24
Peak memory 192136 kb
Host smart-c0fd77b5-0ebd-4b7c-8d52-334785694690
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=537420874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.537420874
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1525061973
Short name T884
Test name
Test status
Simulation time 51114839 ps
CPU time 1.02 seconds
Started May 23 12:41:44 PM PDT 24
Finished May 23 12:41:46 PM PDT 24
Peak memory 198464 kb
Host smart-6c748d1a-5966-40ab-b7c3-1c95c7215bae
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525061973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1525061973
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2309976170
Short name T876
Test name
Test status
Simulation time 298517127 ps
CPU time 0.89 seconds
Started May 23 12:41:39 PM PDT 24
Finished May 23 12:41:42 PM PDT 24
Peak memory 196592 kb
Host smart-e9117e2c-dcb0-4133-b869-798411d94f45
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2309976170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.2309976170
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2682976781
Short name T935
Test name
Test status
Simulation time 144642789 ps
CPU time 1.16 seconds
Started May 23 12:41:37 PM PDT 24
Finished May 23 12:41:40 PM PDT 24
Peak memory 192152 kb
Host smart-f8a8a6d5-d92d-4152-b515-ea2ed0f99f31
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682976781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2682976781
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.3728038118
Short name T899
Test name
Test status
Simulation time 56698832 ps
CPU time 1.11 seconds
Started May 23 12:41:37 PM PDT 24
Finished May 23 12:41:39 PM PDT 24
Peak memory 198464 kb
Host smart-0f4bfec2-8977-4526-b5e3-f59e902fed7e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3728038118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.3728038118
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.429651534
Short name T847
Test name
Test status
Simulation time 229261055 ps
CPU time 1.21 seconds
Started May 23 12:41:39 PM PDT 24
Finished May 23 12:41:42 PM PDT 24
Peak memory 198488 kb
Host smart-1a01ae6e-51a0-4450-845b-aa280dea9c4b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429651534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.429651534
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2095973043
Short name T860
Test name
Test status
Simulation time 44295424 ps
CPU time 1.16 seconds
Started May 23 12:41:39 PM PDT 24
Finished May 23 12:41:42 PM PDT 24
Peak memory 198412 kb
Host smart-718dda13-6ef0-4be2-8fca-29928a768644
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2095973043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.2095973043
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.137960555
Short name T897
Test name
Test status
Simulation time 45512424 ps
CPU time 0.87 seconds
Started May 23 12:41:38 PM PDT 24
Finished May 23 12:41:41 PM PDT 24
Peak memory 192080 kb
Host smart-bf61b5f2-fbf1-480c-9b8a-812184de8f0a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137960555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.137960555
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3753962449
Short name T907
Test name
Test status
Simulation time 40488979 ps
CPU time 1.02 seconds
Started May 23 12:41:39 PM PDT 24
Finished May 23 12:41:42 PM PDT 24
Peak memory 198464 kb
Host smart-cd4484f6-cd22-46af-8516-559ac960a428
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3753962449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.3753962449
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3269748104
Short name T845
Test name
Test status
Simulation time 53059414 ps
CPU time 1.07 seconds
Started May 23 12:41:37 PM PDT 24
Finished May 23 12:41:39 PM PDT 24
Peak memory 192252 kb
Host smart-c80f14cd-b691-417b-8d6c-e63c3f01ed71
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269748104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3269748104
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.72400681
Short name T908
Test name
Test status
Simulation time 133982943 ps
CPU time 1.14 seconds
Started May 23 12:41:39 PM PDT 24
Finished May 23 12:41:42 PM PDT 24
Peak memory 198420 kb
Host smart-6b52678e-7765-4512-9bee-17e1c715284a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=72400681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.72400681
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3907263011
Short name T936
Test name
Test status
Simulation time 74919753 ps
CPU time 1.2 seconds
Started May 23 12:41:47 PM PDT 24
Finished May 23 12:41:49 PM PDT 24
Peak memory 192288 kb
Host smart-e016cd6e-ff4b-402c-9bae-bed7c5808ec3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907263011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3907263011
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3936572584
Short name T938
Test name
Test status
Simulation time 100598935 ps
CPU time 0.88 seconds
Started May 23 12:41:24 PM PDT 24
Finished May 23 12:41:27 PM PDT 24
Peak memory 191936 kb
Host smart-bbd74007-7d10-460b-a76e-2af11a14cc44
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3936572584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.3936572584
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2699802859
Short name T867
Test name
Test status
Simulation time 153392723 ps
CPU time 1.07 seconds
Started May 23 12:41:24 PM PDT 24
Finished May 23 12:41:28 PM PDT 24
Peak memory 192120 kb
Host smart-da9751f5-d93a-4e4e-907d-3690bce3e0d2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699802859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2699802859
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1530418190
Short name T865
Test name
Test status
Simulation time 167736385 ps
CPU time 1.3 seconds
Started May 23 12:41:24 PM PDT 24
Finished May 23 12:41:27 PM PDT 24
Peak memory 192116 kb
Host smart-c8330be3-ff61-45ee-b0b8-4fda454a6411
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1530418190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.1530418190
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.489496031
Short name T848
Test name
Test status
Simulation time 113874051 ps
CPU time 1.17 seconds
Started May 23 12:41:23 PM PDT 24
Finished May 23 12:41:26 PM PDT 24
Peak memory 197032 kb
Host smart-c0d10778-1b27-4594-8d53-828eff2c136f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489496031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.489496031
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3871467334
Short name T885
Test name
Test status
Simulation time 157265283 ps
CPU time 1.27 seconds
Started May 23 12:41:24 PM PDT 24
Finished May 23 12:41:28 PM PDT 24
Peak memory 196792 kb
Host smart-e6f492d0-4cad-4e68-99d0-50c4bb9fd307
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3871467334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.3871467334
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2853352071
Short name T866
Test name
Test status
Simulation time 77914653 ps
CPU time 0.97 seconds
Started May 23 12:41:25 PM PDT 24
Finished May 23 12:41:28 PM PDT 24
Peak memory 196632 kb
Host smart-a42413d2-a420-413d-aafa-129a38775479
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853352071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2853352071
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.683526026
Short name T934
Test name
Test status
Simulation time 60064986 ps
CPU time 1.01 seconds
Started May 23 12:41:23 PM PDT 24
Finished May 23 12:41:26 PM PDT 24
Peak memory 192100 kb
Host smart-780d19b6-db29-4795-a8a9-672216c8ff83
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=683526026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.683526026
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.708684017
Short name T898
Test name
Test status
Simulation time 160666318 ps
CPU time 1.33 seconds
Started May 23 12:41:22 PM PDT 24
Finished May 23 12:41:24 PM PDT 24
Peak memory 192284 kb
Host smart-686a2b03-98c7-488d-838b-3453a88f2bf6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708684017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.708684017
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2879675484
Short name T939
Test name
Test status
Simulation time 50787560 ps
CPU time 0.94 seconds
Started May 23 12:41:24 PM PDT 24
Finished May 23 12:41:27 PM PDT 24
Peak memory 198504 kb
Host smart-d7ff5ba7-9999-415d-9fc2-69e0a5a4c685
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2879675484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.2879675484
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2823657346
Short name T844
Test name
Test status
Simulation time 46745970 ps
CPU time 1.11 seconds
Started May 23 12:41:24 PM PDT 24
Finished May 23 12:41:27 PM PDT 24
Peak memory 192248 kb
Host smart-2c0c7773-febe-41c7-9853-c69832527db8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823657346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2823657346
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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