Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4789319	1			T20	1		T1	473		T11	1
all_pins[1]	4789319	1			T20	1		T1	473		T11	1
all_pins[2]	4789319	1			T20	1		T1	473		T11	1
all_pins[3]	4789319	1			T20	1		T1	473		T11	1
all_pins[4]	4789319	1			T20	1		T1	473		T11	1
all_pins[5]	4789319	1			T20	1		T1	473		T11	1
all_pins[6]	4789319	1			T20	1		T1	473		T11	1
all_pins[7]	4789319	1			T20	1		T1	473		T11	1
all_pins[8]	4789319	1			T20	1		T1	473		T11	1
all_pins[9]	4789319	1			T20	1		T1	473		T11	1
all_pins[10]	4789319	1			T20	1		T1	473		T11	1
all_pins[11]	4789319	1			T20	1		T1	473		T11	1
all_pins[12]	4789319	1			T20	1		T1	473		T11	1
all_pins[13]	4789319	1			T20	1		T1	473		T11	1
all_pins[14]	4789319	1			T20	1		T1	473		T11	1
all_pins[15]	4789319	1			T20	1		T1	473		T11	1
all_pins[16]	4789319	1			T20	1		T1	473		T11	1
all_pins[17]	4789319	1			T20	1		T1	473		T11	1
all_pins[18]	4789319	1			T20	1		T1	473		T11	1
all_pins[19]	4789319	1			T20	1		T1	473		T11	1
all_pins[20]	4789319	1			T20	1		T1	473		T11	1
all_pins[21]	4789319	1			T20	1		T1	473		T11	1
all_pins[22]	4789319	1			T20	1		T1	473		T11	1
all_pins[23]	4789319	1			T20	1		T1	473		T11	1
all_pins[24]	4789319	1			T20	1		T1	473		T11	1
all_pins[25]	4789319	1			T20	1		T1	473		T11	1
all_pins[26]	4789319	1			T20	1		T1	473		T11	1
all_pins[27]	4789319	1			T20	1		T1	473		T11	1
all_pins[28]	4789319	1			T20	1		T1	473		T11	1
all_pins[29]	4789319	1			T20	1		T1	473		T11	1
all_pins[30]	4789319	1			T20	1		T1	473		T11	1
all_pins[31]	4789319	1			T20	1		T1	473		T11	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	95204554	1			T20	32		T1	9354		T11	32
values[0x1]	58053654	1			T1	5782		T13	440		T2	324403
transitions[0x0=>0x1]	34793253	1			T1	3473		T13	298		T2	193494
transitions[0x1=>0x0]	34793115	1			T1	3472		T13	298		T2	193494

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2974819	1			T20	1		T1	282		T11	1
all_pins[0]	values[0x1]	1814500	1			T1	191		T13	15		T2	10309
all_pins[0]	transitions[0x0=>0x1]	1121607	1			T1	112		T13	5		T2	6386
all_pins[0]	transitions[0x1=>0x0]	1123728	1			T1	123		T13	19		T2	6223
all_pins[1]	values[0x0]	2977770	1			T20	1		T1	282		T11	1
all_pins[1]	values[0x1]	1811549	1			T1	191		T13	21		T2	10405
all_pins[1]	transitions[0x0=>0x1]	1085947	1			T1	110		T13	14		T2	6280
all_pins[1]	transitions[0x1=>0x0]	1088898	1			T1	110		T13	8		T2	6184
all_pins[2]	values[0x0]	2970649	1			T20	1		T1	324		T11	1
all_pins[2]	values[0x1]	1818670	1			T1	149		T13	8		T2	10566
all_pins[2]	transitions[0x0=>0x1]	1088342	1			T1	93		T13	8		T2	6068
all_pins[2]	transitions[0x1=>0x0]	1081221	1			T1	135		T13	21		T2	5907
all_pins[3]	values[0x0]	2975993	1			T20	1		T1	265		T11	1
all_pins[3]	values[0x1]	1813326	1			T1	208		T13	19		T2	10143
all_pins[3]	transitions[0x0=>0x1]	1087021	1			T1	136		T13	12		T2	5895
all_pins[3]	transitions[0x1=>0x0]	1092365	1			T1	77		T13	1		T2	6318
all_pins[4]	values[0x0]	2968437	1			T20	1		T1	269		T11	1
all_pins[4]	values[0x1]	1820882	1			T1	204		T13	19		T2	9984
all_pins[4]	transitions[0x0=>0x1]	1089553	1			T1	103		T13	16		T2	5822
all_pins[4]	transitions[0x1=>0x0]	1081997	1			T1	107		T13	16		T2	5981
all_pins[5]	values[0x0]	2976788	1			T20	1		T1	308		T11	1
all_pins[5]	values[0x1]	1812531	1			T1	165		T13	14		T2	10403
all_pins[5]	transitions[0x0=>0x1]	1080338	1			T1	104		T13	8		T2	6302
all_pins[5]	transitions[0x1=>0x0]	1088689	1			T1	143		T13	13		T2	5883
all_pins[6]	values[0x0]	2974230	1			T20	1		T1	301		T11	1
all_pins[6]	values[0x1]	1815089	1			T1	172		T13	15		T2	10099
all_pins[6]	transitions[0x0=>0x1]	1087044	1			T1	128		T13	10		T2	5860
all_pins[6]	transitions[0x1=>0x0]	1084486	1			T1	121		T13	9		T2	6164
all_pins[7]	values[0x0]	2971479	1			T20	1		T1	295		T11	1
all_pins[7]	values[0x1]	1817840	1			T1	178		T13	13		T2	10193
all_pins[7]	transitions[0x0=>0x1]	1085731	1			T1	101		T13	7		T2	6273
all_pins[7]	transitions[0x1=>0x0]	1082980	1			T1	95		T13	9		T2	6179
all_pins[8]	values[0x0]	2971823	1			T20	1		T1	292		T11	1
all_pins[8]	values[0x1]	1817496	1			T1	181		T13	29		T2	10236
all_pins[8]	transitions[0x0=>0x1]	1087130	1			T1	117		T13	20		T2	6112
all_pins[8]	transitions[0x1=>0x0]	1087474	1			T1	114		T13	4		T2	6069
all_pins[9]	values[0x0]	2976878	1			T20	1		T1	281		T11	1
all_pins[9]	values[0x1]	1812441	1			T1	192		T13	16		T2	10195
all_pins[9]	transitions[0x0=>0x1]	1085382	1			T1	101		T13	9		T2	5974
all_pins[9]	transitions[0x1=>0x0]	1090437	1			T1	90		T13	22		T2	6015
all_pins[10]	values[0x0]	2971345	1			T20	1		T1	339		T11	1
all_pins[10]	values[0x1]	1817974	1			T1	134		T13	13		T2	9600
all_pins[10]	transitions[0x0=>0x1]	1088953	1			T1	46		T13	5		T2	5651
all_pins[10]	transitions[0x1=>0x0]	1083420	1			T1	104		T13	8		T2	6246
all_pins[11]	values[0x0]	2978918	1			T20	1		T1	244		T11	1
all_pins[11]	values[0x1]	1810401	1			T1	229		T13	5		T2	10069
all_pins[11]	transitions[0x0=>0x1]	1083357	1			T1	165		T13	5		T2	6192
all_pins[11]	transitions[0x1=>0x0]	1090930	1			T1	70		T13	13		T2	5723
all_pins[12]	values[0x0]	2977648	1			T20	1		T1	297		T11	1
all_pins[12]	values[0x1]	1811671	1			T1	176		T13	15		T2	10047
all_pins[12]	transitions[0x0=>0x1]	1083864	1			T1	93		T13	15		T2	5881
all_pins[12]	transitions[0x1=>0x0]	1082594	1			T1	146		T13	5		T2	5903
all_pins[13]	values[0x0]	2974921	1			T20	1		T1	283		T11	1
all_pins[13]	values[0x1]	1814398	1			T1	190		T13	6		T2	10292
all_pins[13]	transitions[0x0=>0x1]	1089221	1			T1	122		T13	4		T2	6163
all_pins[13]	transitions[0x1=>0x0]	1086494	1			T1	108		T13	13		T2	5918
all_pins[14]	values[0x0]	2980329	1			T20	1		T1	311		T11	1
all_pins[14]	values[0x1]	1808990	1			T1	162		T13	8		T2	10321
all_pins[14]	transitions[0x0=>0x1]	1082476	1			T1	69		T13	8		T2	6278
all_pins[14]	transitions[0x1=>0x0]	1087884	1			T1	97		T13	6		T2	6249
all_pins[15]	values[0x0]	2977009	1			T20	1		T1	347		T11	1
all_pins[15]	values[0x1]	1812310	1			T1	126		T13	7		T2	9836
all_pins[15]	transitions[0x0=>0x1]	1085693	1			T1	91		T13	7		T2	5702
all_pins[15]	transitions[0x1=>0x0]	1082373	1			T1	127		T13	8		T2	6187
all_pins[16]	values[0x0]	2981602	1			T20	1		T1	351		T11	1
all_pins[16]	values[0x1]	1807717	1			T1	122		T13	11		T2	9837
all_pins[16]	transitions[0x0=>0x1]	1083834	1			T1	83		T13	11		T2	5828
all_pins[16]	transitions[0x1=>0x0]	1088427	1			T1	87		T13	7		T2	5827
all_pins[17]	values[0x0]	2982921	1			T20	1		T1	272		T11	1
all_pins[17]	values[0x1]	1806398	1			T1	201		T13	36		T2	10203
all_pins[17]	transitions[0x0=>0x1]	1085416	1			T1	153		T13	28		T2	6386
all_pins[17]	transitions[0x1=>0x0]	1086735	1			T1	74		T13	3		T2	6020
all_pins[18]	values[0x0]	2972650	1			T20	1		T1	272		T11	1
all_pins[18]	values[0x1]	1816669	1			T1	201		T13	8		T2	10220
all_pins[18]	transitions[0x0=>0x1]	1093192	1			T1	122		T2	6144		T3	3205
all_pins[18]	transitions[0x1=>0x0]	1082921	1			T1	122		T13	28		T2	6127
all_pins[19]	values[0x0]	2969453	1			T20	1		T1	307		T11	1
all_pins[19]	values[0x1]	1819866	1			T1	166		T13	8		T2	9832
all_pins[19]	transitions[0x0=>0x1]	1086108	1			T1	89		T13	5		T2	5763
all_pins[19]	transitions[0x1=>0x0]	1082911	1			T1	124		T13	5		T2	6151
all_pins[20]	values[0x0]	2976938	1			T20	1		T1	280		T11	1
all_pins[20]	values[0x1]	1812381	1			T1	193		T13	2		T2	10259
all_pins[20]	transitions[0x0=>0x1]	1082016	1			T1	112		T2	6194		T3	3084
all_pins[20]	transitions[0x1=>0x0]	1089501	1			T1	85		T13	6		T2	5767
all_pins[21]	values[0x0]	2976803	1			T20	1		T1	301		T11	1
all_pins[21]	values[0x1]	1812516	1			T1	172		T13	11		T2	10526
all_pins[21]	transitions[0x0=>0x1]	1083432	1			T1	101		T13	11		T2	6136
all_pins[21]	transitions[0x1=>0x0]	1083297	1			T1	122		T13	2		T2	5869
all_pins[22]	values[0x0]	2975954	1			T20	1		T1	264		T11	1
all_pins[22]	values[0x1]	1813365	1			T1	209		T13	15		T2	9955
all_pins[22]	transitions[0x0=>0x1]	1085398	1			T1	122		T13	13		T2	5843
all_pins[22]	transitions[0x1=>0x0]	1084549	1			T1	85		T13	9		T2	6414
all_pins[23]	values[0x0]	2978688	1			T20	1		T1	230		T11	1
all_pins[23]	values[0x1]	1810631	1			T1	243		T13	6		T2	10117
all_pins[23]	transitions[0x0=>0x1]	1083283	1			T1	134		T13	4		T2	5914
all_pins[23]	transitions[0x1=>0x0]	1086017	1			T1	100		T13	13		T2	5752
all_pins[24]	values[0x0]	2973276	1			T20	1		T1	310		T11	1
all_pins[24]	values[0x1]	1816043	1			T1	163		T13	10		T2	9776
all_pins[24]	transitions[0x0=>0x1]	1089708	1			T1	68		T13	10		T2	6020
all_pins[24]	transitions[0x1=>0x0]	1084296	1			T1	148		T13	6		T2	6361
all_pins[25]	values[0x0]	2974500	1			T20	1		T1	288		T11	1
all_pins[25]	values[0x1]	1814819	1			T1	185		T13	8		T2	10245
all_pins[25]	transitions[0x0=>0x1]	1086608	1			T1	120		T13	5		T2	6192
all_pins[25]	transitions[0x1=>0x0]	1087832	1			T1	98		T13	7		T2	5723
all_pins[26]	values[0x0]	2974671	1			T20	1		T1	312		T11	1
all_pins[26]	values[0x1]	1814648	1			T1	161		T13	17		T2	9950
all_pins[26]	transitions[0x0=>0x1]	1085541	1			T1	81		T13	9		T2	5769
all_pins[26]	transitions[0x1=>0x0]	1085712	1			T1	105		T2	6064		T3	3180
all_pins[27]	values[0x0]	2976007	1			T20	1		T1	293		T11	1
all_pins[27]	values[0x1]	1813312	1			T1	180		T13	20		T2	10257
all_pins[27]	transitions[0x0=>0x1]	1085602	1			T1	129		T13	6		T2	6366
all_pins[27]	transitions[0x1=>0x0]	1086938	1			T1	110		T13	3		T2	6059
all_pins[28]	values[0x0]	2973417	1			T20	1		T1	326		T11	1
all_pins[28]	values[0x1]	1815902	1			T1	147		T13	10		T2	10189
all_pins[28]	transitions[0x0=>0x1]	1089453	1			T1	102		T13	6		T2	6120
all_pins[28]	transitions[0x1=>0x0]	1086863	1			T1	135		T13	16		T2	6188
all_pins[29]	values[0x0]	2971859	1			T20	1		T1	257		T11	1
all_pins[29]	values[0x1]	1817460	1			T1	216		T13	8		T2	10251
all_pins[29]	transitions[0x0=>0x1]	1089575	1			T1	151		T13	3		T2	5983
all_pins[29]	transitions[0x1=>0x0]	1088017	1			T1	82		T13	5		T2	5921
all_pins[30]	values[0x0]	2974219	1			T20	1		T1	301		T11	1
all_pins[30]	values[0x1]	1815100	1			T1	172		T13	18		T2	9942
all_pins[30]	transitions[0x0=>0x1]	1084083	1			T1	99		T13	10		T2	5893
all_pins[30]	transitions[0x1=>0x0]	1086443	1			T1	143		T2	6202		T3	2973
all_pins[31]	values[0x0]	2972560	1			T20	1		T1	270		T11	1
all_pins[31]	values[0x1]	1816759	1			T1	203		T13	29		T2	10146
all_pins[31]	transitions[0x0=>0x1]	1088345	1			T1	116		T13	24		T2	6104
all_pins[31]	transitions[0x1=>0x0]	1086686	1			T1	85		T13	13		T2	5900