Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	15680672	1			T20	364		T1	1214		T11	151
all_values[1]	15680672	1			T20	364		T1	1214		T11	151
all_values[2]	15680672	1			T20	364		T1	1214		T11	151
all_values[3]	15680672	1			T20	364		T1	1214		T11	151
all_values[4]	15680672	1			T20	364		T1	1214		T11	151
all_values[5]	15680672	1			T20	364		T1	1214		T11	151
all_values[6]	15680672	1			T20	364		T1	1214		T11	151
all_values[7]	15680672	1			T20	364		T1	1214		T11	151
all_values[8]	15680672	1			T20	364		T1	1214		T11	151
all_values[9]	15680672	1			T20	364		T1	1214		T11	151
all_values[10]	15680672	1			T20	364		T1	1214		T11	151
all_values[11]	15680672	1			T20	364		T1	1214		T11	151
all_values[12]	15680672	1			T20	364		T1	1214		T11	151
all_values[13]	15680672	1			T20	364		T1	1214		T11	151
all_values[14]	15680672	1			T20	364		T1	1214		T11	151
all_values[15]	15680672	1			T20	364		T1	1214		T11	151
all_values[16]	15680672	1			T20	364		T1	1214		T11	151
all_values[17]	15680672	1			T20	364		T1	1214		T11	151
all_values[18]	15680672	1			T20	364		T1	1214		T11	151
all_values[19]	15680672	1			T20	364		T1	1214		T11	151
all_values[20]	15680672	1			T20	364		T1	1214		T11	151
all_values[21]	15680672	1			T20	364		T1	1214		T11	151
all_values[22]	15680672	1			T20	364		T1	1214		T11	151
all_values[23]	15680672	1			T20	364		T1	1214		T11	151
all_values[24]	15680672	1			T20	364		T1	1214		T11	151
all_values[25]	15680672	1			T20	364		T1	1214		T11	151
all_values[26]	15680672	1			T20	364		T1	1214		T11	151
all_values[27]	15680672	1			T20	364		T1	1214		T11	151
all_values[28]	15680672	1			T20	364		T1	1214		T11	151
all_values[29]	15680672	1			T20	364		T1	1214		T11	151
all_values[30]	15680672	1			T20	364		T1	1214		T11	151
all_values[31]	15680672	1			T20	364		T1	1214		T11	151

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

285564514

1

T20

11648

T1

19216

T11

4832

auto[1]

216216990

1

T1

19632

T13

926

T2

125695

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

110717187

1

T20

11648

T1

4797

T11

4832

auto[1]

391064317

1

T1

34051

T13

1473

T2

227636

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

496380984

1

T20

11648

T1

37619

T11

4832

auto[1]

5400520

1

T1

1229

T13

199

T2

40770

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2805255	1			T20	364		T1	48		T11	151
all_values[0]	auto[0]	auto[0]	auto[1]	6005238	1			T1	531		T13	18		T2	34809
all_values[0]	auto[0]	auto[1]	auto[0]	651947	1			T1	52		T13	16		T2	3451
all_values[0]	auto[0]	auto[1]	auto[1]	6049528	1			T1	548		T13	17		T2	35606
all_values[0]	auto[1]	auto[0]	auto[1]	84462	1			T1	18		T13	5		T2	677
all_values[0]	auto[1]	auto[1]	auto[1]	84242	1			T1	17		T13	3		T2	607
all_values[1]	auto[0]	auto[0]	auto[0]	2811065	1			T20	364		T1	38		T11	151
all_values[1]	auto[0]	auto[0]	auto[1]	6032936	1			T1	553		T13	28		T2	34172
all_values[1]	auto[0]	auto[1]	auto[0]	656242	1			T1	84		T13	12		T2	3492
all_values[1]	auto[0]	auto[1]	auto[1]	6011730	1			T1	501		T13	18		T2	36198
all_values[1]	auto[1]	auto[0]	auto[1]	84361	1			T1	22		T13	5		T2	627
all_values[1]	auto[1]	auto[1]	auto[1]	84338	1			T1	16		T13	5		T2	651
all_values[2]	auto[0]	auto[0]	auto[0]	2801223	1			T20	364		T1	63		T11	151
all_values[2]	auto[0]	auto[0]	auto[1]	6008683	1			T1	551		T13	45		T2	34015
all_values[2]	auto[0]	auto[1]	auto[0]	655076	1			T1	82		T13	8		T2	3794
all_values[2]	auto[0]	auto[1]	auto[1]	6046829	1			T1	477		T13	4		T2	35967
all_values[2]	auto[1]	auto[0]	auto[1]	85086	1			T1	24		T13	2		T2	668
all_values[2]	auto[1]	auto[1]	auto[1]	83775	1			T1	17		T13	2		T2	615
all_values[3]	auto[0]	auto[0]	auto[0]	2807534	1			T20	364		T1	39		T11	151
all_values[3]	auto[0]	auto[0]	auto[1]	6025182	1			T1	583		T13	36		T2	35051
all_values[3]	auto[0]	auto[1]	auto[0]	656145	1			T1	66		T13	10		T2	3617
all_values[3]	auto[0]	auto[1]	auto[1]	6022791	1			T1	490		T13	18		T2	34494
all_values[3]	auto[1]	auto[0]	auto[1]	84856	1			T1	18		T13	2		T2	632
all_values[3]	auto[1]	auto[1]	auto[1]	84164	1			T1	18		T13	3		T2	627
all_values[4]	auto[0]	auto[0]	auto[0]	2811022	1			T20	364		T1	79		T11	151
all_values[4]	auto[0]	auto[0]	auto[1]	6028519	1			T1	527		T13	26		T2	35467
all_values[4]	auto[0]	auto[1]	auto[0]	664608	1			T1	36		T13	14		T2	3618
all_values[4]	auto[0]	auto[1]	auto[1]	6007649	1			T1	532		T13	19		T2	34455
all_values[4]	auto[1]	auto[0]	auto[1]	84314	1			T1	17		T13	3		T2	660
all_values[4]	auto[1]	auto[1]	auto[1]	84560	1			T1	23		T13	4		T2	612
all_values[5]	auto[0]	auto[0]	auto[0]	2807431	1			T20	364		T1	47		T11	151
all_values[5]	auto[0]	auto[0]	auto[1]	6021952	1			T1	541		T13	30		T2	34845
all_values[5]	auto[0]	auto[1]	auto[0]	659402	1			T1	68		T13	4		T2	3652
all_values[5]	auto[0]	auto[1]	auto[1]	6022769	1			T1	518		T13	14		T2	35390
all_values[5]	auto[1]	auto[0]	auto[1]	84447	1			T1	21		T13	3		T2	652
all_values[5]	auto[1]	auto[1]	auto[1]	84671	1			T1	19		T13	2		T2	641
all_values[6]	auto[0]	auto[0]	auto[0]	2807505	1			T20	364		T1	63		T11	151
all_values[6]	auto[0]	auto[0]	auto[1]	6015528	1			T1	522		T13	28		T2	35189
all_values[6]	auto[0]	auto[1]	auto[0]	655820	1			T1	116		T13	14		T2	3794
all_values[6]	auto[0]	auto[1]	auto[1]	6033247	1			T1	470		T13	15		T2	34835
all_values[6]	auto[1]	auto[0]	auto[1]	84564	1			T1	23		T13	5		T2	615
all_values[6]	auto[1]	auto[1]	auto[1]	84008	1			T1	20		T13	2		T2	634
all_values[7]	auto[0]	auto[0]	auto[0]	2806516	1			T20	364		T1	77		T11	151
all_values[7]	auto[0]	auto[0]	auto[1]	6009420	1			T1	574		T13	17		T2	35649
all_values[7]	auto[0]	auto[1]	auto[0]	649111	1			T1	67		T13	14		T2	3671
all_values[7]	auto[0]	auto[1]	auto[1]	6046803	1			T1	459		T13	13		T2	34357
all_values[7]	auto[1]	auto[0]	auto[1]	84331	1			T1	18		T13	5		T2	649
all_values[7]	auto[1]	auto[1]	auto[1]	84491	1			T1	19		T13	2		T2	633
all_values[8]	auto[0]	auto[0]	auto[0]	2811708	1			T20	364		T1	70		T11	151
all_values[8]	auto[0]	auto[0]	auto[1]	6028785	1			T1	526		T13	14		T2	35846
all_values[8]	auto[0]	auto[1]	auto[0]	655609	1			T1	60		T13	7		T2	3611
all_values[8]	auto[0]	auto[1]	auto[1]	6016147	1			T1	525		T13	30		T2	34251
all_values[8]	auto[1]	auto[0]	auto[1]	84497	1			T1	18		T13	3		T2	616
all_values[8]	auto[1]	auto[1]	auto[1]	83926	1			T1	15		T13	4		T2	608
all_values[9]	auto[0]	auto[0]	auto[0]	2814492	1			T20	364		T1	109		T11	151
all_values[9]	auto[0]	auto[0]	auto[1]	6012358	1			T1	478		T13	37		T2	35253
all_values[9]	auto[0]	auto[1]	auto[0]	652475	1			T1	52		T13	23		T2	3479
all_values[9]	auto[0]	auto[1]	auto[1]	6032736	1			T1	541		T13	14		T2	34800
all_values[9]	auto[1]	auto[0]	auto[1]	84951	1			T1	11		T13	2		T2	685
all_values[9]	auto[1]	auto[1]	auto[1]	83660	1			T1	23		T13	3		T2	655
all_values[10]	auto[0]	auto[0]	auto[0]	2803801	1			T20	364		T1	59		T11	151
all_values[10]	auto[0]	auto[0]	auto[1]	6035188	1			T1	621		T13	32		T2	35963
all_values[10]	auto[0]	auto[1]	auto[0]	658366	1			T1	61		T13	14		T2	3533
all_values[10]	auto[0]	auto[1]	auto[1]	6014350	1			T1	428		T13	14		T2	34221
all_values[10]	auto[1]	auto[0]	auto[1]	84412	1			T1	27		T13	5		T2	670
all_values[10]	auto[1]	auto[1]	auto[1]	84555	1			T1	18		T2	597		T3	409
all_values[11]	auto[0]	auto[0]	auto[0]	2814852	1			T20	364		T1	55		T11	151
all_values[11]	auto[0]	auto[0]	auto[1]	6040989	1			T1	398		T13	31		T2	35597
all_values[11]	auto[0]	auto[1]	auto[0]	653943	1			T1	97		T13	8		T2	3598
all_values[11]	auto[0]	auto[1]	auto[1]	6002406	1			T1	628		T13	5		T2	34636
all_values[11]	auto[1]	auto[0]	auto[1]	84498	1			T1	12		T13	6		T2	614
all_values[11]	auto[1]	auto[1]	auto[1]	83984	1			T1	24		T2	674		T3	435
all_values[12]	auto[0]	auto[0]	auto[0]	2804836	1			T20	364		T1	101		T11	151
all_values[12]	auto[0]	auto[0]	auto[1]	6045742	1			T1	565		T13	16		T2	34752
all_values[12]	auto[0]	auto[1]	auto[0]	658580	1			T1	103		T13	25		T2	4027
all_values[12]	auto[0]	auto[1]	auto[1]	6002315	1			T1	406		T13	14		T2	34916
all_values[12]	auto[1]	auto[0]	auto[1]	85106	1			T1	21		T13	2		T2	624
all_values[12]	auto[1]	auto[1]	auto[1]	84093	1			T1	18		T13	4		T2	625
all_values[13]	auto[0]	auto[0]	auto[0]	2797001	1			T20	364		T1	91		T11	151
all_values[13]	auto[0]	auto[0]	auto[1]	6060963	1			T1	489		T13	28		T2	33679
all_values[13]	auto[0]	auto[1]	auto[0]	648765	1			T1	33		T13	12		T2	4358
all_values[13]	auto[0]	auto[1]	auto[1]	6005377	1			T1	559		T13	6		T2	35547
all_values[13]	auto[1]	auto[0]	auto[1]	84549	1			T1	20		T13	4		T2	625
all_values[13]	auto[1]	auto[1]	auto[1]	84017	1			T1	22		T2	686		T3	399
all_values[14]	auto[0]	auto[0]	auto[0]	2822920	1			T20	364		T1	135		T11	151
all_values[14]	auto[0]	auto[0]	auto[1]	6002088	1			T1	475		T13	13		T2	34276
all_values[14]	auto[0]	auto[1]	auto[0]	648761	1			T1	103		T13	29		T2	3819
all_values[14]	auto[0]	auto[1]	auto[1]	6037722	1			T1	462		T13	7		T2	35651
all_values[14]	auto[1]	auto[0]	auto[1]	84783	1			T1	16		T13	4		T2	635
all_values[14]	auto[1]	auto[1]	auto[1]	84398	1			T1	23		T13	2		T2	619
all_values[15]	auto[0]	auto[0]	auto[0]	2810133	1			T20	364		T1	110		T11	151
all_values[15]	auto[0]	auto[0]	auto[1]	6009659	1			T1	587		T13	43		T2	36862
all_values[15]	auto[0]	auto[1]	auto[0]	651508	1			T1	76		T2	3808		T3	1954
all_values[15]	auto[0]	auto[1]	auto[1]	6040490	1			T1	405		T13	7		T2	33122
all_values[15]	auto[1]	auto[0]	auto[1]	84110	1			T1	20		T13	6		T2	657
all_values[15]	auto[1]	auto[1]	auto[1]	84772	1			T1	16		T13	2		T2	565
all_values[16]	auto[0]	auto[0]	auto[0]	2806710	1			T20	364		T1	129		T11	151
all_values[16]	auto[0]	auto[0]	auto[1]	6056472	1			T1	681		T13	12		T2	35357
all_values[16]	auto[0]	auto[1]	auto[0]	650145	1			T1	40		T13	17		T2	3608
all_values[16]	auto[0]	auto[1]	auto[1]	5998458	1			T1	328		T13	7		T2	34381
all_values[16]	auto[1]	auto[0]	auto[1]	84608	1			T1	22		T13	2		T2	654
all_values[16]	auto[1]	auto[1]	auto[1]	84279	1			T1	14		T13	3		T2	638
all_values[17]	auto[0]	auto[0]	auto[0]	2812704	1			T20	364		T1	79		T11	151
all_values[17]	auto[0]	auto[0]	auto[1]	6034871	1			T1	430		T13	9		T2	34675
all_values[17]	auto[0]	auto[1]	auto[0]	657259	1			T1	63		T13	12		T2	3611
all_values[17]	auto[0]	auto[1]	auto[1]	6007451	1			T1	598		T13	36		T2	35424
all_values[17]	auto[1]	auto[0]	auto[1]	84696	1			T1	18		T13	4		T2	672
all_values[17]	auto[1]	auto[1]	auto[1]	83691	1			T1	26		T13	4		T2	578
all_values[18]	auto[0]	auto[0]	auto[0]	2817081	1			T20	364		T1	100		T11	151
all_values[18]	auto[0]	auto[0]	auto[1]	6042563	1			T1	390		T13	45		T2	34165
all_values[18]	auto[0]	auto[1]	auto[0]	646738	1			T1	78		T13	20		T2	4068
all_values[18]	auto[0]	auto[1]	auto[1]	6005569	1			T1	607		T13	7		T2	35451
all_values[18]	auto[1]	auto[0]	auto[1]	84454	1			T1	20		T13	3		T2	629
all_values[18]	auto[1]	auto[1]	auto[1]	84267	1			T1	19		T13	1		T2	631
all_values[19]	auto[0]	auto[0]	auto[0]	2804785	1			T20	364		T1	80		T11	151
all_values[19]	auto[0]	auto[0]	auto[1]	6038165	1			T1	497		T13	33		T2	35517
all_values[19]	auto[0]	auto[1]	auto[0]	645830	1			T1	63		T13	13		T2	3645
all_values[19]	auto[0]	auto[1]	auto[1]	6023207	1			T1	535		T13	9		T2	34478
all_values[19]	auto[1]	auto[0]	auto[1]	84201	1			T1	23		T13	6		T2	632
all_values[19]	auto[1]	auto[1]	auto[1]	84484	1			T1	16		T13	1		T2	609
all_values[20]	auto[0]	auto[0]	auto[0]	2807061	1			T20	364		T1	75		T11	151
all_values[20]	auto[0]	auto[0]	auto[1]	6040062	1			T1	457		T13	32		T2	33058
all_values[20]	auto[0]	auto[1]	auto[0]	647847	1			T1	110		T13	7		T2	3935
all_values[20]	auto[0]	auto[1]	auto[1]	6016558	1			T1	538		T13	2		T2	36542
all_values[20]	auto[1]	auto[0]	auto[1]	84769	1			T1	18		T13	6		T2	603
all_values[20]	auto[1]	auto[1]	auto[1]	84375	1			T1	16		T13	1		T2	627
all_values[21]	auto[0]	auto[0]	auto[0]	2804094	1			T20	364		T1	67		T11	151
all_values[21]	auto[0]	auto[0]	auto[1]	6050423	1			T1	483		T13	30		T2	34456
all_values[21]	auto[0]	auto[1]	auto[0]	640019	1			T1	95		T13	12		T2	3696
all_values[21]	auto[0]	auto[1]	auto[1]	6017194	1			T1	532		T13	14		T2	35268
all_values[21]	auto[1]	auto[0]	auto[1]	85066	1			T1	15		T13	6		T2	657
all_values[21]	auto[1]	auto[1]	auto[1]	83876	1			T1	22		T13	1		T2	655
all_values[22]	auto[0]	auto[0]	auto[0]	2813280	1			T20	364		T1	43		T11	151
all_values[22]	auto[0]	auto[0]	auto[1]	6023479	1			T1	444		T13	13		T2	35456
all_values[22]	auto[0]	auto[1]	auto[0]	646963	1			T1	67		T13	10		T2	4069
all_values[22]	auto[0]	auto[1]	auto[1]	6028435	1			T1	618		T13	13		T2	34064
all_values[22]	auto[1]	auto[0]	auto[1]	84457	1			T1	20		T13	6		T2	594
all_values[22]	auto[1]	auto[1]	auto[1]	84058	1			T1	22		T13	2		T2	659
all_values[23]	auto[0]	auto[0]	auto[0]	2800072	1			T20	364		T1	48		T11	151
all_values[23]	auto[0]	auto[0]	auto[1]	6060371	1			T1	283		T13	33		T2	35274
all_values[23]	auto[0]	auto[1]	auto[0]	653758	1			T1	80		T13	1		T2	3949
all_values[23]	auto[0]	auto[1]	auto[1]	5997621	1			T1	765		T13	8		T2	34327
all_values[23]	auto[1]	auto[0]	auto[1]	84668	1			T1	11		T13	7		T2	645
all_values[23]	auto[1]	auto[1]	auto[1]	84182	1			T1	27		T2	592		T3	343
all_values[24]	auto[0]	auto[0]	auto[0]	2814733	1			T20	364		T1	86		T11	151
all_values[24]	auto[0]	auto[0]	auto[1]	6008857	1			T1	498		T13	28		T2	36549
all_values[24]	auto[0]	auto[1]	auto[0]	650738	1			T1	92		T13	17		T2	3610
all_values[24]	auto[0]	auto[1]	auto[1]	6037345	1			T1	501		T13	8		T2	33376
all_values[24]	auto[1]	auto[0]	auto[1]	84710	1			T1	14		T13	5		T2	657
all_values[24]	auto[1]	auto[1]	auto[1]	84289	1			T1	23		T13	2		T2	665
all_values[25]	auto[0]	auto[0]	auto[0]	2803307	1			T20	364		T1	73		T11	151
all_values[25]	auto[0]	auto[0]	auto[1]	6028726	1			T1	505		T13	32		T2	33637
all_values[25]	auto[0]	auto[1]	auto[0]	644493	1			T1	92		T13	12		T2	4017
all_values[25]	auto[0]	auto[1]	auto[1]	6035419	1			T1	507		T13	9		T2	35849
all_values[25]	auto[1]	auto[0]	auto[1]	83949	1			T1	18		T13	1		T2	647
all_values[25]	auto[1]	auto[1]	auto[1]	84778	1			T1	19		T13	1		T2	632
all_values[26]	auto[0]	auto[0]	auto[0]	2800247	1			T20	364		T1	67		T11	151
all_values[26]	auto[0]	auto[0]	auto[1]	6056720	1			T1	594		T13	24		T2	35755
all_values[26]	auto[0]	auto[1]	auto[0]	653058	1			T1	63		T13	23		T2	3419
all_values[26]	auto[0]	auto[1]	auto[1]	6002896	1			T1	450		T13	14		T2	34303
all_values[26]	auto[1]	auto[0]	auto[1]	84474	1			T1	18		T13	5		T2	663
all_values[26]	auto[1]	auto[1]	auto[1]	83277	1			T1	22		T13	4		T2	556
all_values[27]	auto[0]	auto[0]	auto[0]	2796037	1			T20	364		T1	101		T11	151
all_values[27]	auto[0]	auto[0]	auto[1]	6052131	1			T1	527		T13	34		T2	33678
all_values[27]	auto[0]	auto[1]	auto[0]	649989	1			T1	45		T13	12		T2	3811
all_values[27]	auto[0]	auto[1]	auto[1]	6013798	1			T1	500		T13	18		T2	36199
all_values[27]	auto[1]	auto[0]	auto[1]	84476	1			T1	16		T13	3		T2	621
all_values[27]	auto[1]	auto[1]	auto[1]	84241	1			T1	25		T13	3		T2	674
all_values[28]	auto[0]	auto[0]	auto[0]	2805234	1			T20	364		T1	117		T11	151
all_values[28]	auto[0]	auto[0]	auto[1]	6080770	1			T1	597		T13	12		T2	34783
all_values[28]	auto[0]	auto[1]	auto[0]	650958	1			T1	54		T13	24		T2	3691
all_values[28]	auto[0]	auto[1]	auto[1]	5974673	1			T1	405		T13	10		T2	35162
all_values[28]	auto[1]	auto[0]	auto[1]	84418	1			T1	22		T13	4		T2	673
all_values[28]	auto[1]	auto[1]	auto[1]	84619	1			T1	19		T13	2		T2	612
all_values[29]	auto[0]	auto[0]	auto[0]	2815452	1			T20	364		T1	58		T11	151
all_values[29]	auto[0]	auto[0]	auto[1]	6028649	1			T1	303		T13	27		T2	34475
all_values[29]	auto[0]	auto[1]	auto[0]	649545	1			T1	143		T13	14		T2	3689
all_values[29]	auto[0]	auto[1]	auto[1]	6018140	1			T1	673		T13	7		T2	34800
all_values[29]	auto[1]	auto[0]	auto[1]	84122	1			T1	11		T13	4		T2	632
all_values[29]	auto[1]	auto[1]	auto[1]	84764	1			T1	26		T13	2		T2	701
all_values[30]	auto[0]	auto[0]	auto[0]	2798268	1			T20	364		T1	47		T11	151
all_values[30]	auto[0]	auto[0]	auto[1]	6019084	1			T1	584		T13	28		T2	34917
all_values[30]	auto[0]	auto[1]	auto[0]	649592	1			T1	64		T13	16		T2	3750
all_values[30]	auto[0]	auto[1]	auto[1]	6044786	1			T1	489		T13	18		T2	34292
all_values[30]	auto[1]	auto[0]	auto[1]	85051	1			T1	19		T13	3		T2	697
all_values[30]	auto[1]	auto[1]	auto[1]	83891	1			T1	11		T13	2		T2	636
all_values[31]	auto[0]	auto[0]	auto[0]	2811012	1			T20	364		T1	45		T11	151
all_values[31]	auto[0]	auto[0]	auto[1]	6006917	1			T1	436		T13	23		T2	35143
all_values[31]	auto[0]	auto[1]	auto[0]	656526	1			T1	93		T13	18		T2	3646
all_values[31]	auto[0]	auto[1]	auto[1]	6037868	1			T1	597		T13	22		T2	34914
all_values[31]	auto[1]	auto[0]	auto[1]	84207	1			T1	16		T13	1		T2	644
all_values[31]	auto[1]	auto[1]	auto[1]	84142	1			T1	27		T13	4		T2	630

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal