Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[1]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[2]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[3]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[4]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[5]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[6]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[7]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[8]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[9]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[10]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[11]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[12]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[13]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[14]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[15]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[16]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[17]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[18]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[19]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[20]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[21]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[22]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[23]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[24]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[25]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[26]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[27]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[28]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[29]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[30]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[31]	15404837	1			T20	702		T1	1120		T11	296

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

297605449

1

T20

17758

T1

8149

T11

2292

auto[1]

195349335

1

T20

4706

T1

27691

T11

7180

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

395501988

1

T20

17087

T1

21608

T11

6772

auto[1]

97452796

1

T20

5377

T1

14232

T11

2700

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

367063291

1

T20

10992

T1

17649

T11

4698

auto[1]

125891493

1

T20

11472

T1

18191

T11

4774

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	5773391	1			T20	277		T1	32		T11	5
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	4162409	1			T20	32		T1	352		T11	50
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1528231	1			T20	100		T1	237		T11	43
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1990428	1			T20	190		T1	15		T11	13
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	424020	1			T20	29		T1	218		T11	122
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1526358	1			T20	74		T1	266		T11	63
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	5774340	1			T20	208		T1	16		T11	9
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	4164242	1			T20	38		T1	250		T11	74
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1532725	1			T20	109		T1	300		T11	20
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1991265	1			T20	216		T1	22		T11	20
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	425938	1			T20	30		T1	305		T11	114
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1516327	1			T20	101		T1	227		T11	59
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	5768625	1			T20	218		T1	19		T11	24
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	4168936	1			T20	16		T1	228		T11	90
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1529974	1			T20	82		T1	291		T11	55
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1991713	1			T20	289		T1	21		T11	8
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	425469	1			T20	46		T1	276		T11	79
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1520120	1			T20	51		T1	285		T11	40
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	5771503	1			T20	266		T1	10		T11	5
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	4167415	1			T20	33		T1	306		T11	40
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1535049	1			T20	92		T1	119		T11	22
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1986969	1			T20	210		T1	24		T11	28
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	422761	1			T20	27		T1	408		T11	120
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1521140	1			T20	74		T1	253		T11	81
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	5770353	1			T20	254		T1	19		T11	22
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	4164617	1			T20	24		T1	354		T11	83
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1528347	1			T20	71		T1	181		T11	65
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1989888	1			T20	262		T1	15		T11	3
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	426118	1			T20	40		T1	362		T11	90
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1525514	1			T20	51		T1	189		T11	33
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	5786471	1			T20	221		T1	12		T11	31
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	4151894	1			T20	34		T1	278		T11	67
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1529043	1			T20	75		T1	177		T11	64
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1989544	1			T20	271		T1	30		T11	3
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	426036	1			T20	32		T1	374		T11	88
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1521849	1			T20	69		T1	249		T11	43
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	5776080	1			T20	202		T1	15		T11	5
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	4162943	1			T20	24		T1	276		T11	43
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1534589	1			T20	90		T1	265		T11	39
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1989296	1			T20	239		T1	22		T11	21
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	424263	1			T20	28		T1	308		T11	134
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1517666	1			T20	119		T1	234		T11	54
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	5772250	1			T20	254		T1	24		T11	4
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	4161751	1			T20	24		T1	320		T11	64
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1532088	1			T20	51		T1	186		T11	42
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1994536	1			T20	245		T1	10		T11	20
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	425141	1			T20	36		T1	331		T11	133
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1519071	1			T20	92		T1	249		T11	33
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	5780412	1			T20	302		T1	14		T11	11
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	4162380	1			T20	37		T1	314		T11	74
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1532589	1			T20	83		T1	201		T11	28
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1987699	1			T20	168		T1	11		T11	15
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	424151	1			T20	14		T1	366		T11	121
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1517606	1			T20	98		T1	214		T11	47
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	5779346	1			T20	240		T1	11		T11	5
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	4162316	1			T20	22		T1	241		T11	104
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1528784	1			T20	76		T1	228		T11	63
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1992225	1			T20	216		T1	21		T11	18
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	424025	1			T20	36		T1	401		T11	73
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1518141	1			T20	112		T1	218		T11	33
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	5767890	1			T20	145		T1	22		T11	5
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	4169261	1			T20	13		T1	335		T11	75
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1532620	1			T20	56		T1	255		T11	40
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1992711	1			T20	318		T1	15		T11	18
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	427842	1			T20	47		T1	269		T11	128
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1514513	1			T20	123		T1	224		T11	30
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	5797420	1			T20	223		T1	14		T11	21
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	4148962	1			T20	50		T1	356		T11	100
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1536618	1			T20	70		T1	267		T11	60
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1982935	1			T20	264		T1	15		T11	14
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	425604	1			T20	18		T1	333		T11	58
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1513298	1			T20	77		T1	135		T11	43
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	5780634	1			T20	252		T1	8		T11	9
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	4155160	1			T20	28		T1	274		T11	118
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1529812	1			T20	103		T1	187		T11	25
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1994725	1			T20	219		T1	22		T11	7
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	426707	1			T20	24		T1	416		T11	115
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1517799	1			T20	76		T1	213		T11	22
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	5780219	1			T20	174		T1	10		T11	11
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	4155013	1			T20	23		T1	420		T11	112
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1535937	1			T20	71		T1	228		T11	38
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1987532	1			T20	322		T1	23		T11	22
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	424101	1			T20	38		T1	321		T11	75
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1522035	1			T20	74		T1	118		T11	38
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	5779729	1			T20	249		T1	18		T11	11
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	4158942	1			T20	21		T1	313		T11	82
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1536913	1			T20	89		T1	176		T11	32
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1987292	1			T20	257		T1	16		T11	13
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	422685	1			T20	39		T1	344		T11	113
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1519276	1			T20	47		T1	253		T11	45
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	5774190	1			T20	250		T1	22		T11	7
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	4158987	1			T20	30		T1	390		T11	116
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1527735	1			T20	78		T1	313		T11	16
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1994261	1			T20	234		T1	11		T11	16
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	425404	1			T20	28		T1	228		T11	108
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1524260	1			T20	82		T1	156		T11	33
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	5776676	1			T20	213		T1	10		T11	27
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	4168178	1			T20	33		T1	345		T11	139
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1524707	1			T20	72		T1	250		T11	69
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1996056	1			T20	244		T1	22		T11	4
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	425470	1			T20	36		T1	295		T11	29
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1513750	1			T20	104		T1	198		T11	28
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	5781357	1			T20	193		T1	15		T11	7
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	4164382	1			T20	18		T1	391		T11	87
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1524687	1			T20	87		T1	190		T11	63
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1995081	1			T20	273		T1	14		T11	22
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	423026	1			T20	39		T1	319		T11	89
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1516304	1			T20	92		T1	191		T11	28
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	5786901	1			T20	205		T1	11		T11	3
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	4158827	1			T20	25		T1	228		T11	77
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1524388	1			T20	79		T1	175		T11	36
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1997769	1			T20	255		T1	22		T11	20
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	425293	1			T20	32		T1	440		T11	115
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1511659	1			T20	106		T1	244		T11	45
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	5779604	1			T20	281		T1	16		T11	16
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	4168216	1			T20	35		T1	268		T11	91
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1528069	1			T20	98		T1	214		T11	54
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1989878	1			T20	192		T1	19		T11	16
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	424361	1			T20	29		T1	324		T11	85
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1514709	1			T20	67		T1	279		T11	34
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	5777013	1			T20	280		T1	8		T11	17
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	4165594	1			T20	46		T1	266		T11	105
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1525035	1			T20	123		T1	236		T11	65
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1994430	1			T20	161		T1	25		T11	5
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	425216	1			T20	15		T1	336		T11	76
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1517549	1			T20	77		T1	249		T11	28
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	5776716	1			T20	179		T1	8		T11	13
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	4163684	1			T20	27		T1	332		T11	101
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1527323	1			T20	82		T1	186		T11	73
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1999672	1			T20	282		T1	22		T11	12
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	426646	1			T20	36		T1	369		T11	61
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1510796	1			T20	96		T1	203		T11	36
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	5790807	1			T20	250		T1	21		T11	5
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	4155503	1			T20	29		T1	336		T11	57
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1530627	1			T20	81		T1	212		T11	60
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1989078	1			T20	217		T1	16		T11	18
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	426558	1			T20	39		T1	240		T11	119
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1512264	1			T20	86		T1	295		T11	37
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	5776937	1			T20	260		T1	21		T11	8
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	4168210	1			T20	31		T1	404		T11	98
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1526729	1			T20	98		T1	187		T11	48
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1996686	1			T20	185		T1	8		T11	17
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	426989	1			T20	29		T1	308		T11	85
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1509286	1			T20	99		T1	192		T11	40
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	5781185	1			T20	208		T1	28		T11	16
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	4165613	1			T20	18		T1	364		T11	124
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1534564	1			T20	67		T1	197		T11	53
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1990296	1			T20	255		T1	12		T11	7
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	425055	1			T20	32		T1	361		T11	69
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1508124	1			T20	122		T1	158		T11	27
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	5783218	1			T20	196		T1	20		T11	23
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	4165925	1			T20	28		T1	293		T11	135
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1526790	1			T20	82		T1	346		T11	24
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1997144	1			T20	273		T1	15		T11	2
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	424260	1			T20	34		T1	238		T11	74
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1507500	1			T20	89		T1	208		T11	38
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	5774989	1			T20	223		T1	15		T11	19
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	4170094	1			T20	51		T1	306		T11	102
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1523417	1			T20	80		T1	244		T11	78
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1996715	1			T20	222		T1	15		T11	9
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	428361	1			T20	22		T1	274		T11	74
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1511261	1			T20	104		T1	266		T11	14
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	5773942	1			T20	193		T1	15		T11	18
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	4166730	1			T20	17		T1	273		T11	82
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1527497	1			T20	42		T1	168		T11	47
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1998879	1			T20	284		T1	15		T11	16
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	425386	1			T20	36		T1	371		T11	106
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1512403	1			T20	130		T1	278		T11	27
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	5773832	1			T20	234		T1	13		T11	2
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	4170895	1			T20	31		T1	288		T11	117
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1523802	1			T20	83		T1	206		T11	39
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1995237	1			T20	252		T1	20		T11	16
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	426111	1			T20	33		T1	340		T11	98
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1514960	1			T20	69		T1	253		T11	24
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	5777456	1			T20	275		T1	13		T11	20
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	4163999	1			T20	35		T1	362		T11	80
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1526045	1			T20	74		T1	225		T11	33
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1995269	1			T20	232		T1	16		T11	7
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	427362	1			T20	24		T1	308		T11	105
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1514706	1			T20	62		T1	196		T11	51
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	5791292	1			T20	261		T1	25		T11	11
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	4164214	1			T20	48		T1	300		T11	137
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1523343	1			T20	87		T1	179		T11	30
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1990977	1			T20	204		T1	13		T11	15
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	426107	1			T20	23		T1	368		T11	81
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1508904	1			T20	79		T1	235		T11	22
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	5768056	1			T20	254		T1	32		T11	7
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	4167317	1			T20	20		T1	295		T11	34
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1529771	1			T20	80		T1	228		T11	19
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1998581	1			T20	256		T1	11		T11	27
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	425312	1			T20	28		T1	304		T11	128
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1515800	1			T20	64		T1	250		T11	81

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal