Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[1]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[2]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[3]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[4]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[5]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[6]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[7]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[8]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[9]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[10]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[11]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[12]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[13]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[14]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[15]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[16]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[17]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[18]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[19]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[20]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[21]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[22]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[23]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[24]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[25]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[26]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[27]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[28]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[29]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[30]	15404837	1			T20	702		T1	1120		T11	296
bins_for_gpio_bits[31]	15404837	1			T20	702		T1	1120		T11	296

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

297605449

1

T20

17758

T1

8149

T11

2292

auto[1]

195349335

1

T20

4706

T1

27691

T11

7180

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

297597627

1

T20

17758

T1

8149

T11

2302

auto[1]

195357157

1

T20

4706

T1

27691

T11

7170

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	9018695	1			T20	551		T1	245		T11	54
bins_for_gpio_bits[0]	auto[0]	auto[1]	273100	1			T20	16		T1	39		T11	8
bins_for_gpio_bits[0]	auto[1]	auto[0]	273355	1			T20	16		T1	39		T11	7
bins_for_gpio_bits[0]	auto[1]	auto[1]	5839687	1			T20	119		T1	797		T11	227
bins_for_gpio_bits[1]	auto[0]	auto[0]	9025724	1			T20	514		T1	303		T11	46
bins_for_gpio_bits[1]	auto[0]	auto[1]	272387	1			T20	19		T1	35		T11	3
bins_for_gpio_bits[1]	auto[1]	auto[0]	272606	1			T20	19		T1	35		T11	3
bins_for_gpio_bits[1]	auto[1]	auto[1]	5834120	1			T20	150		T1	747		T11	244
bins_for_gpio_bits[2]	auto[0]	auto[0]	9017487	1			T20	577		T1	296		T11	81
bins_for_gpio_bits[2]	auto[0]	auto[1]	272550	1			T20	12		T1	35		T11	6
bins_for_gpio_bits[2]	auto[1]	auto[0]	272825	1			T20	12		T1	35		T11	6
bins_for_gpio_bits[2]	auto[1]	auto[1]	5841975	1			T20	101		T1	754		T11	203
bins_for_gpio_bits[3]	auto[0]	auto[0]	9020051	1			T20	555		T1	129		T11	50
bins_for_gpio_bits[3]	auto[0]	auto[1]	273210	1			T20	13		T1	24		T11	5
bins_for_gpio_bits[3]	auto[1]	auto[0]	273470	1			T20	13		T1	24		T11	5
bins_for_gpio_bits[3]	auto[1]	auto[1]	5838106	1			T20	121		T1	943		T11	236
bins_for_gpio_bits[4]	auto[0]	auto[0]	9015022	1			T20	575		T1	188		T11	78
bins_for_gpio_bits[4]	auto[0]	auto[1]	273301	1			T20	12		T1	27		T11	12
bins_for_gpio_bits[4]	auto[1]	auto[0]	273566	1			T20	12		T1	27		T11	12
bins_for_gpio_bits[4]	auto[1]	auto[1]	5842948	1			T20	103		T1	878		T11	194
bins_for_gpio_bits[5]	auto[0]	auto[0]	9031947	1			T20	552		T1	188		T11	89
bins_for_gpio_bits[5]	auto[0]	auto[1]	272859	1			T20	15		T1	31		T11	10
bins_for_gpio_bits[5]	auto[1]	auto[0]	273111	1			T20	15		T1	31		T11	9
bins_for_gpio_bits[5]	auto[1]	auto[1]	5826920	1			T20	120		T1	870		T11	188
bins_for_gpio_bits[6]	auto[0]	auto[0]	9026837	1			T20	512		T1	269		T11	59
bins_for_gpio_bits[6]	auto[0]	auto[1]	272907	1			T20	19		T1	33		T11	7
bins_for_gpio_bits[6]	auto[1]	auto[0]	273128	1			T20	19		T1	33		T11	6
bins_for_gpio_bits[6]	auto[1]	auto[1]	5831965	1			T20	152		T1	785		T11	224
bins_for_gpio_bits[7]	auto[0]	auto[0]	9024986	1			T20	534		T1	191		T11	60
bins_for_gpio_bits[7]	auto[0]	auto[1]	273632	1			T20	16		T1	29		T11	7
bins_for_gpio_bits[7]	auto[1]	auto[0]	273888	1			T20	16		T1	29		T11	6
bins_for_gpio_bits[7]	auto[1]	auto[1]	5832331	1			T20	136		T1	871		T11	223
bins_for_gpio_bits[8]	auto[0]	auto[0]	9027572	1			T20	536		T1	201		T11	48
bins_for_gpio_bits[8]	auto[0]	auto[1]	272864	1			T20	17		T1	25		T11	6
bins_for_gpio_bits[8]	auto[1]	auto[0]	273128	1			T20	17		T1	25		T11	6
bins_for_gpio_bits[8]	auto[1]	auto[1]	5831273	1			T20	132		T1	869		T11	236
bins_for_gpio_bits[9]	auto[0]	auto[0]	9026759	1			T20	515		T1	226		T11	77
bins_for_gpio_bits[9]	auto[0]	auto[1]	273349	1			T20	17		T1	34		T11	9
bins_for_gpio_bits[9]	auto[1]	auto[0]	273596	1			T20	17		T1	34		T11	9
bins_for_gpio_bits[9]	auto[1]	auto[1]	5831133	1			T20	153		T1	826		T11	201
bins_for_gpio_bits[10]	auto[0]	auto[0]	9020224	1			T20	495		T1	256		T11	55
bins_for_gpio_bits[10]	auto[0]	auto[1]	272760	1			T20	24		T1	36		T11	8
bins_for_gpio_bits[10]	auto[1]	auto[0]	272997	1			T20	24		T1	36		T11	8
bins_for_gpio_bits[10]	auto[1]	auto[1]	5838856	1			T20	159		T1	792		T11	225
bins_for_gpio_bits[11]	auto[0]	auto[0]	9044398	1			T20	545		T1	270		T11	84
bins_for_gpio_bits[11]	auto[0]	auto[1]	272332	1			T20	12		T1	26		T11	11
bins_for_gpio_bits[11]	auto[1]	auto[0]	272575	1			T20	12		T1	26		T11	11
bins_for_gpio_bits[11]	auto[1]	auto[1]	5815532	1			T20	133		T1	798		T11	190
bins_for_gpio_bits[12]	auto[0]	auto[0]	9031804	1			T20	555		T1	193		T11	37
bins_for_gpio_bits[12]	auto[0]	auto[1]	273127	1			T20	19		T1	24		T11	5
bins_for_gpio_bits[12]	auto[1]	auto[0]	273367	1			T20	19		T1	24		T11	4
bins_for_gpio_bits[12]	auto[1]	auto[1]	5826539	1			T20	109		T1	879		T11	250
bins_for_gpio_bits[13]	auto[0]	auto[0]	9029705	1			T20	555		T1	237		T11	64
bins_for_gpio_bits[13]	auto[0]	auto[1]	273705	1			T20	12		T1	24		T11	7
bins_for_gpio_bits[13]	auto[1]	auto[0]	273983	1			T20	12		T1	24		T11	7
bins_for_gpio_bits[13]	auto[1]	auto[1]	5827444	1			T20	123		T1	835		T11	218
bins_for_gpio_bits[14]	auto[0]	auto[0]	9030216	1			T20	585		T1	183		T11	51
bins_for_gpio_bits[14]	auto[0]	auto[1]	273491	1			T20	10		T1	27		T11	6
bins_for_gpio_bits[14]	auto[1]	auto[0]	273718	1			T20	10		T1	27		T11	5
bins_for_gpio_bits[14]	auto[1]	auto[1]	5827412	1			T20	97		T1	883		T11	234
bins_for_gpio_bits[15]	auto[0]	auto[0]	9022644	1			T20	547		T1	310		T11	34
bins_for_gpio_bits[15]	auto[0]	auto[1]	273300	1			T20	15		T1	36		T11	5
bins_for_gpio_bits[15]	auto[1]	auto[0]	273542	1			T20	15		T1	36		T11	5
bins_for_gpio_bits[15]	auto[1]	auto[1]	5835351	1			T20	125		T1	738		T11	252
bins_for_gpio_bits[16]	auto[0]	auto[0]	9024356	1			T20	505		T1	247		T11	90
bins_for_gpio_bits[16]	auto[0]	auto[1]	272814	1			T20	24		T1	35		T11	11
bins_for_gpio_bits[16]	auto[1]	auto[0]	273083	1			T20	24		T1	35		T11	10
bins_for_gpio_bits[16]	auto[1]	auto[1]	5834584	1			T20	149		T1	803		T11	185
bins_for_gpio_bits[17]	auto[0]	auto[0]	9027536	1			T20	537		T1	194		T11	79
bins_for_gpio_bits[17]	auto[0]	auto[1]	273384	1			T20	16		T1	25		T11	13
bins_for_gpio_bits[17]	auto[1]	auto[0]	273589	1			T20	16		T1	25		T11	13
bins_for_gpio_bits[17]	auto[1]	auto[1]	5830328	1			T20	133		T1	876		T11	191
bins_for_gpio_bits[18]	auto[0]	auto[0]	9036004	1			T20	519		T1	185		T11	51
bins_for_gpio_bits[18]	auto[0]	auto[1]	272824	1			T20	20		T1	23		T11	9
bins_for_gpio_bits[18]	auto[1]	auto[0]	273054	1			T20	20		T1	23		T11	8
bins_for_gpio_bits[18]	auto[1]	auto[1]	5822955	1			T20	143		T1	889		T11	228
bins_for_gpio_bits[19]	auto[0]	auto[0]	9023964	1			T20	557		T1	218		T11	77
bins_for_gpio_bits[19]	auto[0]	auto[1]	273352	1			T20	14		T1	31		T11	9
bins_for_gpio_bits[19]	auto[1]	auto[0]	273587	1			T20	14		T1	31		T11	9
bins_for_gpio_bits[19]	auto[1]	auto[1]	5833934	1			T20	117		T1	840		T11	201
bins_for_gpio_bits[20]	auto[0]	auto[0]	9022062	1			T20	549		T1	232		T11	76
bins_for_gpio_bits[20]	auto[0]	auto[1]	274192	1			T20	15		T1	37		T11	11
bins_for_gpio_bits[20]	auto[1]	auto[0]	274416	1			T20	15		T1	37		T11	11
bins_for_gpio_bits[20]	auto[1]	auto[1]	5834167	1			T20	123		T1	814		T11	198
bins_for_gpio_bits[21]	auto[0]	auto[0]	9030736	1			T20	523		T1	184		T11	86
bins_for_gpio_bits[21]	auto[0]	auto[1]	272753	1			T20	20		T1	32		T11	13
bins_for_gpio_bits[21]	auto[1]	auto[0]	272975	1			T20	20		T1	32		T11	12
bins_for_gpio_bits[21]	auto[1]	auto[1]	5828373	1			T20	139		T1	872		T11	185
bins_for_gpio_bits[22]	auto[0]	auto[0]	9036701	1			T20	533		T1	218		T11	75
bins_for_gpio_bits[22]	auto[0]	auto[1]	273558	1			T20	15		T1	31		T11	8
bins_for_gpio_bits[22]	auto[1]	auto[0]	273811	1			T20	15		T1	31		T11	8
bins_for_gpio_bits[22]	auto[1]	auto[1]	5820767	1			T20	139		T1	840		T11	205
bins_for_gpio_bits[23]	auto[0]	auto[0]	9027355	1			T20	523		T1	188		T11	64
bins_for_gpio_bits[23]	auto[0]	auto[1]	272751	1			T20	20		T1	28		T11	9
bins_for_gpio_bits[23]	auto[1]	auto[0]	272997	1			T20	20		T1	28		T11	9
bins_for_gpio_bits[23]	auto[1]	auto[1]	5831734	1			T20	139		T1	876		T11	214
bins_for_gpio_bits[24]	auto[0]	auto[0]	9032568	1			T20	511		T1	207		T11	62
bins_for_gpio_bits[24]	auto[0]	auto[1]	273211	1			T20	19		T1	30		T11	15
bins_for_gpio_bits[24]	auto[1]	auto[0]	273477	1			T20	19		T1	30		T11	14
bins_for_gpio_bits[24]	auto[1]	auto[1]	5825581	1			T20	153		T1	853		T11	205
bins_for_gpio_bits[25]	auto[0]	auto[0]	9034332	1			T20	533		T1	344		T11	43
bins_for_gpio_bits[25]	auto[0]	auto[1]	272542	1			T20	18		T1	37		T11	6
bins_for_gpio_bits[25]	auto[1]	auto[0]	272820	1			T20	18		T1	37		T11	6
bins_for_gpio_bits[25]	auto[1]	auto[1]	5825143	1			T20	133		T1	702		T11	241
bins_for_gpio_bits[26]	auto[0]	auto[0]	9021904	1			T20	508		T1	237		T11	95
bins_for_gpio_bits[26]	auto[0]	auto[1]	272991	1			T20	17		T1	37		T11	11
bins_for_gpio_bits[26]	auto[1]	auto[0]	273217	1			T20	17		T1	37		T11	11
bins_for_gpio_bits[26]	auto[1]	auto[1]	5836725	1			T20	160		T1	809		T11	179
bins_for_gpio_bits[27]	auto[0]	auto[0]	9026905	1			T20	495		T1	167		T11	73
bins_for_gpio_bits[27]	auto[0]	auto[1]	273151	1			T20	24		T1	31		T11	8
bins_for_gpio_bits[27]	auto[1]	auto[0]	273413	1			T20	24		T1	31		T11	8
bins_for_gpio_bits[27]	auto[1]	auto[1]	5831368	1			T20	159		T1	891		T11	207
bins_for_gpio_bits[28]	auto[0]	auto[0]	9019602	1			T20	555		T1	207		T11	49
bins_for_gpio_bits[28]	auto[0]	auto[1]	273059	1			T20	14		T1	32		T11	8
bins_for_gpio_bits[28]	auto[1]	auto[0]	273269	1			T20	14		T1	32		T11	8
bins_for_gpio_bits[28]	auto[1]	auto[1]	5838907	1			T20	119		T1	849		T11	231
bins_for_gpio_bits[29]	auto[0]	auto[0]	9025661	1			T20	568		T1	221		T11	55
bins_for_gpio_bits[29]	auto[0]	auto[1]	272873	1			T20	13		T1	33		T11	5
bins_for_gpio_bits[29]	auto[1]	auto[0]	273109	1			T20	13		T1	33		T11	5
bins_for_gpio_bits[29]	auto[1]	auto[1]	5833194	1			T20	108		T1	833		T11	231
bins_for_gpio_bits[30]	auto[0]	auto[0]	9033066	1			T20	535		T1	183		T11	49
bins_for_gpio_bits[30]	auto[0]	auto[1]	272326	1			T20	17		T1	34		T11	7
bins_for_gpio_bits[30]	auto[1]	auto[0]	272546	1			T20	17		T1	34		T11	7
bins_for_gpio_bits[30]	auto[1]	auto[1]	5826899	1			T20	133		T1	869		T11	233
bins_for_gpio_bits[31]	auto[0]	auto[0]	9021827	1			T20	574		T1	237		T11	48
bins_for_gpio_bits[31]	auto[0]	auto[1]	274322	1			T20	16		T1	34		T11	5
bins_for_gpio_bits[31]	auto[1]	auto[0]	274581	1			T20	16		T1	34		T11	5
bins_for_gpio_bits[31]	auto[1]	auto[1]	5834107	1			T20	96		T1	815		T11	238