Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8894955 |
1 |
|
|
T20 |
364 |
|
T1 |
597 |
|
T11 |
151 |
| auto[1] |
6785717 |
1 |
|
|
T1 |
617 |
|
T13 |
36 |
|
T2 |
39664 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14806832 |
1 |
|
|
T20 |
364 |
|
T1 |
1184 |
|
T11 |
151 |
| auto[1] |
873840 |
1 |
|
|
T1 |
30 |
|
T13 |
2 |
|
T2 |
4670 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8941815 |
1 |
|
|
T20 |
364 |
|
T1 |
599 |
|
T11 |
151 |
| auto[1] |
6738857 |
1 |
|
|
T1 |
615 |
|
T13 |
18 |
|
T2 |
39358 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2919857 |
1 |
|
|
T1 |
248 |
|
T13 |
9 |
|
T2 |
17469 |
| auto[1] |
auto[0] |
auto[1] |
434919 |
1 |
|
|
T1 |
11 |
|
T13 |
1 |
|
T2 |
2248 |
| auto[1] |
auto[1] |
auto[0] |
2945160 |
1 |
|
|
T1 |
337 |
|
T13 |
7 |
|
T2 |
17219 |
| auto[1] |
auto[1] |
auto[1] |
438921 |
1 |
|
|
T1 |
19 |
|
T13 |
1 |
|
T2 |
2422 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8928362 |
1 |
|
|
T20 |
364 |
|
T1 |
613 |
|
T11 |
151 |
| auto[1] |
6752310 |
1 |
|
|
T1 |
601 |
|
T13 |
35 |
|
T2 |
40341 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14799819 |
1 |
|
|
T20 |
364 |
|
T1 |
1186 |
|
T11 |
151 |
| auto[1] |
880853 |
1 |
|
|
T1 |
28 |
|
T13 |
2 |
|
T2 |
4582 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8879181 |
1 |
|
|
T20 |
364 |
|
T1 |
601 |
|
T11 |
151 |
| auto[1] |
6801491 |
1 |
|
|
T1 |
613 |
|
T13 |
32 |
|
T2 |
39077 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2971318 |
1 |
|
|
T1 |
246 |
|
T13 |
21 |
|
T2 |
16494 |
| auto[1] |
auto[0] |
auto[1] |
441580 |
1 |
|
|
T1 |
14 |
|
T13 |
2 |
|
T2 |
2156 |
| auto[1] |
auto[1] |
auto[0] |
2949320 |
1 |
|
|
T1 |
339 |
|
T13 |
9 |
|
T2 |
18001 |
| auto[1] |
auto[1] |
auto[1] |
439273 |
1 |
|
|
T1 |
14 |
|
T2 |
2426 |
|
T3 |
1098 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8923401 |
1 |
|
|
T20 |
364 |
|
T1 |
707 |
|
T11 |
151 |
| auto[1] |
6757271 |
1 |
|
|
T1 |
507 |
|
T13 |
28 |
|
T2 |
38351 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14809788 |
1 |
|
|
T20 |
364 |
|
T1 |
1180 |
|
T11 |
151 |
| auto[1] |
870884 |
1 |
|
|
T1 |
34 |
|
T13 |
1 |
|
T2 |
4715 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8955210 |
1 |
|
|
T20 |
364 |
|
T1 |
552 |
|
T11 |
151 |
| auto[1] |
6725462 |
1 |
|
|
T1 |
662 |
|
T13 |
37 |
|
T2 |
39504 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2934383 |
1 |
|
|
T1 |
405 |
|
T13 |
18 |
|
T2 |
18723 |
| auto[1] |
auto[0] |
auto[1] |
436999 |
1 |
|
|
T1 |
23 |
|
T13 |
1 |
|
T2 |
2514 |
| auto[1] |
auto[1] |
auto[0] |
2920195 |
1 |
|
|
T1 |
223 |
|
T13 |
18 |
|
T2 |
16066 |
| auto[1] |
auto[1] |
auto[1] |
433885 |
1 |
|
|
T1 |
11 |
|
T2 |
2201 |
|
T3 |
1058 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8940339 |
1 |
|
|
T20 |
364 |
|
T1 |
465 |
|
T11 |
151 |
| auto[1] |
6740333 |
1 |
|
|
T1 |
749 |
|
T13 |
13 |
|
T2 |
38908 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14804761 |
1 |
|
|
T20 |
364 |
|
T1 |
1194 |
|
T11 |
151 |
| auto[1] |
875911 |
1 |
|
|
T1 |
20 |
|
T13 |
1 |
|
T2 |
4850 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8919951 |
1 |
|
|
T20 |
364 |
|
T1 |
638 |
|
T11 |
151 |
| auto[1] |
6760721 |
1 |
|
|
T1 |
576 |
|
T13 |
35 |
|
T2 |
40003 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2953905 |
1 |
|
|
T1 |
155 |
|
T13 |
27 |
|
T2 |
17652 |
| auto[1] |
auto[0] |
auto[1] |
440400 |
1 |
|
|
T1 |
8 |
|
T13 |
1 |
|
T2 |
2478 |
| auto[1] |
auto[1] |
auto[0] |
2930905 |
1 |
|
|
T1 |
401 |
|
T13 |
7 |
|
T2 |
17501 |
| auto[1] |
auto[1] |
auto[1] |
435511 |
1 |
|
|
T1 |
12 |
|
T2 |
2372 |
|
T3 |
1087 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8935684 |
1 |
|
|
T20 |
364 |
|
T1 |
687 |
|
T11 |
151 |
| auto[1] |
6744988 |
1 |
|
|
T1 |
527 |
|
T13 |
43 |
|
T2 |
39568 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14804626 |
1 |
|
|
T20 |
364 |
|
T1 |
1200 |
|
T11 |
151 |
| auto[1] |
876046 |
1 |
|
|
T1 |
14 |
|
T13 |
1 |
|
T2 |
4404 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8918557 |
1 |
|
|
T20 |
364 |
|
T1 |
737 |
|
T11 |
151 |
| auto[1] |
6762115 |
1 |
|
|
T1 |
477 |
|
T13 |
48 |
|
T2 |
38117 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2957972 |
1 |
|
|
T1 |
219 |
|
T13 |
19 |
|
T2 |
16857 |
| auto[1] |
auto[0] |
auto[1] |
441415 |
1 |
|
|
T1 |
4 |
|
T13 |
1 |
|
T2 |
2232 |
| auto[1] |
auto[1] |
auto[0] |
2928097 |
1 |
|
|
T1 |
244 |
|
T13 |
28 |
|
T2 |
16856 |
| auto[1] |
auto[1] |
auto[1] |
434631 |
1 |
|
|
T1 |
10 |
|
T2 |
2172 |
|
T3 |
1165 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8942513 |
1 |
|
|
T20 |
364 |
|
T1 |
600 |
|
T11 |
151 |
| auto[1] |
6738159 |
1 |
|
|
T1 |
614 |
|
T13 |
18 |
|
T2 |
40591 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14803227 |
1 |
|
|
T20 |
364 |
|
T1 |
1198 |
|
T11 |
151 |
| auto[1] |
877445 |
1 |
|
|
T1 |
16 |
|
T13 |
1 |
|
T2 |
4409 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8915422 |
1 |
|
|
T20 |
364 |
|
T1 |
685 |
|
T11 |
151 |
| auto[1] |
6765250 |
1 |
|
|
T1 |
529 |
|
T13 |
26 |
|
T2 |
37688 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2967266 |
1 |
|
|
T1 |
263 |
|
T13 |
19 |
|
T2 |
15893 |
| auto[1] |
auto[0] |
auto[1] |
442512 |
1 |
|
|
T1 |
10 |
|
T2 |
1992 |
|
T3 |
1227 |
| auto[1] |
auto[1] |
auto[0] |
2920539 |
1 |
|
|
T1 |
250 |
|
T13 |
6 |
|
T2 |
17386 |
| auto[1] |
auto[1] |
auto[1] |
434933 |
1 |
|
|
T1 |
6 |
|
T13 |
1 |
|
T2 |
2417 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8909791 |
1 |
|
|
T20 |
364 |
|
T1 |
626 |
|
T11 |
151 |
| auto[1] |
6770881 |
1 |
|
|
T1 |
588 |
|
T13 |
38 |
|
T2 |
40089 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14803791 |
1 |
|
|
T20 |
364 |
|
T1 |
1187 |
|
T11 |
151 |
| auto[1] |
876881 |
1 |
|
|
T1 |
27 |
|
T2 |
4783 |
|
T3 |
2374 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8917327 |
1 |
|
|
T20 |
364 |
|
T1 |
566 |
|
T11 |
151 |
| auto[1] |
6763345 |
1 |
|
|
T1 |
648 |
|
T13 |
27 |
|
T2 |
39706 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2933714 |
1 |
|
|
T1 |
327 |
|
T13 |
11 |
|
T2 |
16865 |
| auto[1] |
auto[0] |
auto[1] |
436683 |
1 |
|
|
T1 |
9 |
|
T2 |
2255 |
|
T3 |
1183 |
| auto[1] |
auto[1] |
auto[0] |
2952750 |
1 |
|
|
T1 |
294 |
|
T13 |
16 |
|
T2 |
18058 |
| auto[1] |
auto[1] |
auto[1] |
440198 |
1 |
|
|
T1 |
18 |
|
T2 |
2528 |
|
T3 |
1191 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8903902 |
1 |
|
|
T20 |
364 |
|
T1 |
717 |
|
T11 |
151 |
| auto[1] |
6776770 |
1 |
|
|
T1 |
497 |
|
T13 |
9 |
|
T2 |
37495 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14805174 |
1 |
|
|
T20 |
364 |
|
T1 |
1190 |
|
T11 |
151 |
| auto[1] |
875498 |
1 |
|
|
T1 |
24 |
|
T2 |
4562 |
|
T3 |
2215 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8929605 |
1 |
|
|
T20 |
364 |
|
T1 |
562 |
|
T11 |
151 |
| auto[1] |
6751067 |
1 |
|
|
T1 |
652 |
|
T13 |
47 |
|
T2 |
38422 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2945212 |
1 |
|
|
T1 |
358 |
|
T13 |
38 |
|
T2 |
17669 |
| auto[1] |
auto[0] |
auto[1] |
439810 |
1 |
|
|
T1 |
14 |
|
T2 |
2385 |
|
T3 |
1128 |
| auto[1] |
auto[1] |
auto[0] |
2930357 |
1 |
|
|
T1 |
270 |
|
T13 |
9 |
|
T2 |
16191 |
| auto[1] |
auto[1] |
auto[1] |
435688 |
1 |
|
|
T1 |
10 |
|
T2 |
2177 |
|
T3 |
1087 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8947790 |
1 |
|
|
T20 |
364 |
|
T1 |
832 |
|
T11 |
151 |
| auto[1] |
6732882 |
1 |
|
|
T1 |
382 |
|
T13 |
27 |
|
T2 |
38627 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14805692 |
1 |
|
|
T20 |
364 |
|
T1 |
1191 |
|
T11 |
151 |
| auto[1] |
874980 |
1 |
|
|
T1 |
23 |
|
T13 |
1 |
|
T2 |
4516 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8936378 |
1 |
|
|
T20 |
364 |
|
T1 |
702 |
|
T11 |
151 |
| auto[1] |
6744294 |
1 |
|
|
T1 |
512 |
|
T13 |
41 |
|
T2 |
39534 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2953985 |
1 |
|
|
T1 |
340 |
|
T13 |
31 |
|
T2 |
17940 |
| auto[1] |
auto[0] |
auto[1] |
440447 |
1 |
|
|
T1 |
16 |
|
T13 |
1 |
|
T2 |
2301 |
| auto[1] |
auto[1] |
auto[0] |
2915329 |
1 |
|
|
T1 |
149 |
|
T13 |
9 |
|
T2 |
17078 |
| auto[1] |
auto[1] |
auto[1] |
434533 |
1 |
|
|
T1 |
7 |
|
T2 |
2215 |
|
T3 |
1283 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8932271 |
1 |
|
|
T20 |
364 |
|
T1 |
527 |
|
T11 |
151 |
| auto[1] |
6748401 |
1 |
|
|
T1 |
687 |
|
T13 |
52 |
|
T2 |
39613 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14807081 |
1 |
|
|
T20 |
364 |
|
T1 |
1196 |
|
T11 |
151 |
| auto[1] |
873591 |
1 |
|
|
T1 |
18 |
|
T2 |
4505 |
|
T3 |
2170 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8930254 |
1 |
|
|
T20 |
364 |
|
T1 |
528 |
|
T11 |
151 |
| auto[1] |
6750418 |
1 |
|
|
T1 |
686 |
|
T13 |
34 |
|
T2 |
38759 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2938418 |
1 |
|
|
T1 |
246 |
|
T13 |
17 |
|
T2 |
16786 |
| auto[1] |
auto[0] |
auto[1] |
436123 |
1 |
|
|
T1 |
7 |
|
T2 |
2188 |
|
T3 |
989 |
| auto[1] |
auto[1] |
auto[0] |
2938409 |
1 |
|
|
T1 |
422 |
|
T13 |
17 |
|
T2 |
17468 |
| auto[1] |
auto[1] |
auto[1] |
437468 |
1 |
|
|
T1 |
11 |
|
T2 |
2317 |
|
T3 |
1181 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8944098 |
1 |
|
|
T20 |
364 |
|
T1 |
510 |
|
T11 |
151 |
| auto[1] |
6736574 |
1 |
|
|
T1 |
704 |
|
T13 |
28 |
|
T2 |
40150 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14803905 |
1 |
|
|
T20 |
364 |
|
T1 |
1194 |
|
T11 |
151 |
| auto[1] |
876767 |
1 |
|
|
T1 |
20 |
|
T2 |
4603 |
|
T3 |
2202 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8909972 |
1 |
|
|
T20 |
364 |
|
T1 |
609 |
|
T11 |
151 |
| auto[1] |
6770700 |
1 |
|
|
T1 |
605 |
|
T13 |
32 |
|
T2 |
39673 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2954913 |
1 |
|
|
T1 |
245 |
|
T13 |
23 |
|
T2 |
17020 |
| auto[1] |
auto[0] |
auto[1] |
439509 |
1 |
|
|
T1 |
7 |
|
T2 |
2151 |
|
T3 |
1115 |
| auto[1] |
auto[1] |
auto[0] |
2939020 |
1 |
|
|
T1 |
340 |
|
T13 |
9 |
|
T2 |
18050 |
| auto[1] |
auto[1] |
auto[1] |
437258 |
1 |
|
|
T1 |
13 |
|
T2 |
2452 |
|
T3 |
1087 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8927151 |
1 |
|
|
T20 |
364 |
|
T1 |
600 |
|
T11 |
151 |
| auto[1] |
6753521 |
1 |
|
|
T1 |
614 |
|
T13 |
23 |
|
T2 |
38732 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14805296 |
1 |
|
|
T20 |
364 |
|
T1 |
1197 |
|
T11 |
151 |
| auto[1] |
875376 |
1 |
|
|
T1 |
17 |
|
T13 |
1 |
|
T2 |
4390 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8924777 |
1 |
|
|
T20 |
364 |
|
T1 |
589 |
|
T11 |
151 |
| auto[1] |
6755895 |
1 |
|
|
T1 |
625 |
|
T13 |
38 |
|
T2 |
38141 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2937977 |
1 |
|
|
T1 |
341 |
|
T13 |
28 |
|
T2 |
16467 |
| auto[1] |
auto[0] |
auto[1] |
437224 |
1 |
|
|
T1 |
11 |
|
T13 |
1 |
|
T2 |
2166 |
| auto[1] |
auto[1] |
auto[0] |
2942542 |
1 |
|
|
T1 |
267 |
|
T13 |
9 |
|
T2 |
17284 |
| auto[1] |
auto[1] |
auto[1] |
438152 |
1 |
|
|
T1 |
6 |
|
T2 |
2224 |
|
T3 |
1186 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8894992 |
1 |
|
|
T20 |
364 |
|
T1 |
638 |
|
T11 |
151 |
| auto[1] |
6785680 |
1 |
|
|
T1 |
576 |
|
T13 |
14 |
|
T2 |
40376 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14801291 |
1 |
|
|
T20 |
364 |
|
T1 |
1183 |
|
T11 |
151 |
| auto[1] |
879381 |
1 |
|
|
T1 |
31 |
|
T2 |
4544 |
|
T3 |
2335 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8906728 |
1 |
|
|
T20 |
364 |
|
T1 |
521 |
|
T11 |
151 |
| auto[1] |
6773944 |
1 |
|
|
T1 |
693 |
|
T13 |
24 |
|
T2 |
38679 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2935820 |
1 |
|
|
T1 |
344 |
|
T13 |
24 |
|
T2 |
16661 |
| auto[1] |
auto[0] |
auto[1] |
437028 |
1 |
|
|
T1 |
17 |
|
T2 |
2231 |
|
T3 |
1127 |
| auto[1] |
auto[1] |
auto[0] |
2958743 |
1 |
|
|
T1 |
318 |
|
T2 |
17474 |
|
T3 |
9165 |
| auto[1] |
auto[1] |
auto[1] |
442353 |
1 |
|
|
T1 |
14 |
|
T2 |
2313 |
|
T3 |
1208 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8931892 |
1 |
|
|
T20 |
364 |
|
T1 |
550 |
|
T11 |
151 |
| auto[1] |
6748780 |
1 |
|
|
T1 |
664 |
|
T13 |
10 |
|
T2 |
41104 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14804528 |
1 |
|
|
T20 |
364 |
|
T1 |
1186 |
|
T11 |
151 |
| auto[1] |
876144 |
1 |
|
|
T1 |
28 |
|
T13 |
1 |
|
T2 |
4747 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8919131 |
1 |
|
|
T20 |
364 |
|
T1 |
583 |
|
T11 |
151 |
| auto[1] |
6761541 |
1 |
|
|
T1 |
631 |
|
T13 |
45 |
|
T2 |
40122 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2952043 |
1 |
|
|
T1 |
317 |
|
T13 |
41 |
|
T2 |
17200 |
| auto[1] |
auto[0] |
auto[1] |
439365 |
1 |
|
|
T1 |
16 |
|
T2 |
2247 |
|
T3 |
1211 |
| auto[1] |
auto[1] |
auto[0] |
2933354 |
1 |
|
|
T1 |
286 |
|
T13 |
3 |
|
T2 |
18175 |
| auto[1] |
auto[1] |
auto[1] |
436779 |
1 |
|
|
T1 |
12 |
|
T13 |
1 |
|
T2 |
2500 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8939583 |
1 |
|
|
T20 |
364 |
|
T1 |
565 |
|
T11 |
151 |
| auto[1] |
6741089 |
1 |
|
|
T1 |
649 |
|
T13 |
27 |
|
T2 |
39619 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14805767 |
1 |
|
|
T20 |
364 |
|
T1 |
1192 |
|
T11 |
151 |
| auto[1] |
874905 |
1 |
|
|
T1 |
22 |
|
T13 |
1 |
|
T2 |
4780 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8929036 |
1 |
|
|
T20 |
364 |
|
T1 |
600 |
|
T11 |
151 |
| auto[1] |
6751636 |
1 |
|
|
T1 |
614 |
|
T13 |
39 |
|
T2 |
39755 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2953977 |
1 |
|
|
T1 |
301 |
|
T13 |
27 |
|
T2 |
17305 |
| auto[1] |
auto[0] |
auto[1] |
439875 |
1 |
|
|
T1 |
8 |
|
T2 |
2322 |
|
T3 |
1030 |
| auto[1] |
auto[1] |
auto[0] |
2922754 |
1 |
|
|
T1 |
291 |
|
T13 |
11 |
|
T2 |
17670 |
| auto[1] |
auto[1] |
auto[1] |
435030 |
1 |
|
|
T1 |
14 |
|
T13 |
1 |
|
T2 |
2458 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8921216 |
1 |
|
|
T20 |
364 |
|
T1 |
507 |
|
T11 |
151 |
| auto[1] |
6759456 |
1 |
|
|
T1 |
707 |
|
T13 |
25 |
|
T2 |
38792 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14805747 |
1 |
|
|
T20 |
364 |
|
T1 |
1189 |
|
T11 |
151 |
| auto[1] |
874925 |
1 |
|
|
T1 |
25 |
|
T13 |
2 |
|
T2 |
4831 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8928056 |
1 |
|
|
T20 |
364 |
|
T1 |
679 |
|
T11 |
151 |
| auto[1] |
6752616 |
1 |
|
|
T1 |
535 |
|
T13 |
18 |
|
T2 |
40445 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2924372 |
1 |
|
|
T1 |
199 |
|
T13 |
11 |
|
T2 |
18254 |
| auto[1] |
auto[0] |
auto[1] |
433665 |
1 |
|
|
T1 |
6 |
|
T13 |
2 |
|
T2 |
2549 |
| auto[1] |
auto[1] |
auto[0] |
2953319 |
1 |
|
|
T1 |
311 |
|
T13 |
5 |
|
T2 |
17360 |
| auto[1] |
auto[1] |
auto[1] |
441260 |
1 |
|
|
T1 |
19 |
|
T2 |
2282 |
|
T3 |
1196 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8945111 |
1 |
|
|
T20 |
364 |
|
T1 |
342 |
|
T11 |
151 |
| auto[1] |
6735561 |
1 |
|
|
T1 |
872 |
|
T13 |
9 |
|
T2 |
38868 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14801706 |
1 |
|
|
T20 |
364 |
|
T1 |
1192 |
|
T11 |
151 |
| auto[1] |
878966 |
1 |
|
|
T1 |
22 |
|
T13 |
1 |
|
T2 |
4673 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8902649 |
1 |
|
|
T20 |
364 |
|
T1 |
552 |
|
T11 |
151 |
| auto[1] |
6778023 |
1 |
|
|
T1 |
662 |
|
T13 |
28 |
|
T2 |
39783 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2958200 |
1 |
|
|
T1 |
182 |
|
T13 |
27 |
|
T2 |
17573 |
| auto[1] |
auto[0] |
auto[1] |
440683 |
1 |
|
|
T1 |
9 |
|
T13 |
1 |
|
T2 |
2278 |
| auto[1] |
auto[1] |
auto[0] |
2940857 |
1 |
|
|
T1 |
458 |
|
T2 |
17537 |
|
T3 |
9235 |
| auto[1] |
auto[1] |
auto[1] |
438283 |
1 |
|
|
T1 |
13 |
|
T2 |
2395 |
|
T3 |
1169 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8908300 |
1 |
|
|
T20 |
364 |
|
T1 |
598 |
|
T11 |
151 |
| auto[1] |
6772372 |
1 |
|
|
T1 |
616 |
|
T13 |
27 |
|
T2 |
37651 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14805274 |
1 |
|
|
T20 |
364 |
|
T1 |
1188 |
|
T11 |
151 |
| auto[1] |
875398 |
1 |
|
|
T1 |
26 |
|
T13 |
1 |
|
T2 |
4628 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8933895 |
1 |
|
|
T20 |
364 |
|
T1 |
595 |
|
T11 |
151 |
| auto[1] |
6746777 |
1 |
|
|
T1 |
619 |
|
T13 |
29 |
|
T2 |
39516 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2937772 |
1 |
|
|
T1 |
246 |
|
T13 |
16 |
|
T2 |
17725 |
| auto[1] |
auto[0] |
auto[1] |
437116 |
1 |
|
|
T1 |
12 |
|
T13 |
1 |
|
T2 |
2302 |
| auto[1] |
auto[1] |
auto[0] |
2933607 |
1 |
|
|
T1 |
347 |
|
T13 |
12 |
|
T2 |
17163 |
| auto[1] |
auto[1] |
auto[1] |
438282 |
1 |
|
|
T1 |
14 |
|
T2 |
2326 |
|
T3 |
1084 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8915982 |
1 |
|
|
T20 |
364 |
|
T1 |
596 |
|
T11 |
151 |
| auto[1] |
6764690 |
1 |
|
|
T1 |
618 |
|
T13 |
22 |
|
T2 |
40498 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14800759 |
1 |
|
|
T20 |
364 |
|
T1 |
1187 |
|
T11 |
151 |
| auto[1] |
879913 |
1 |
|
|
T1 |
27 |
|
T2 |
4503 |
|
T3 |
2203 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8894286 |
1 |
|
|
T20 |
364 |
|
T1 |
547 |
|
T11 |
151 |
| auto[1] |
6786386 |
1 |
|
|
T1 |
667 |
|
T13 |
37 |
|
T2 |
38796 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2957880 |
1 |
|
|
T1 |
302 |
|
T13 |
17 |
|
T2 |
16933 |
| auto[1] |
auto[0] |
auto[1] |
441176 |
1 |
|
|
T1 |
18 |
|
T2 |
2241 |
|
T3 |
1006 |
| auto[1] |
auto[1] |
auto[0] |
2948593 |
1 |
|
|
T1 |
338 |
|
T13 |
20 |
|
T2 |
17360 |
| auto[1] |
auto[1] |
auto[1] |
438737 |
1 |
|
|
T1 |
9 |
|
T2 |
2262 |
|
T3 |
1197 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8941441 |
1 |
|
|
T20 |
364 |
|
T1 |
679 |
|
T11 |
151 |
| auto[1] |
6739231 |
1 |
|
|
T1 |
535 |
|
T13 |
41 |
|
T2 |
38278 |