Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8913830 |
1 |
|
|
T20 |
364 |
|
T1 |
609 |
|
T11 |
151 |
| auto[1] |
6766842 |
1 |
|
|
T1 |
605 |
|
T13 |
20 |
|
T2 |
39683 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14805668 |
1 |
|
|
T20 |
364 |
|
T1 |
1191 |
|
T11 |
151 |
| auto[1] |
875004 |
1 |
|
|
T1 |
23 |
|
T13 |
1 |
|
T2 |
4343 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8923278 |
1 |
|
|
T20 |
364 |
|
T1 |
524 |
|
T11 |
151 |
| auto[1] |
6757394 |
1 |
|
|
T1 |
690 |
|
T13 |
37 |
|
T2 |
37781 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2927834 |
1 |
|
|
T1 |
303 |
|
T13 |
27 |
|
T2 |
16427 |
| auto[1] |
auto[0] |
auto[1] |
434844 |
1 |
|
|
T1 |
11 |
|
T13 |
1 |
|
T2 |
2221 |
| auto[1] |
auto[1] |
auto[0] |
2954556 |
1 |
|
|
T1 |
364 |
|
T13 |
9 |
|
T2 |
17011 |
| auto[1] |
auto[1] |
auto[1] |
440160 |
1 |
|
|
T1 |
12 |
|
T2 |
2122 |
|
T3 |
1196 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |