Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8907597 |
1 |
|
|
T20 |
364 |
|
T1 |
608 |
|
T11 |
151 |
| auto[1] |
6773075 |
1 |
|
|
T1 |
606 |
|
T13 |
31 |
|
T2 |
39263 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14803566 |
1 |
|
|
T20 |
364 |
|
T1 |
1194 |
|
T11 |
151 |
| auto[1] |
877106 |
1 |
|
|
T1 |
20 |
|
T2 |
4635 |
|
T3 |
2293 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8919693 |
1 |
|
|
T20 |
364 |
|
T1 |
647 |
|
T11 |
151 |
| auto[1] |
6760979 |
1 |
|
|
T1 |
567 |
|
T13 |
40 |
|
T2 |
38670 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2944995 |
1 |
|
|
T1 |
295 |
|
T13 |
30 |
|
T2 |
16875 |
| auto[1] |
auto[0] |
auto[1] |
439118 |
1 |
|
|
T1 |
7 |
|
T2 |
2317 |
|
T3 |
1195 |
| auto[1] |
auto[1] |
auto[0] |
2938878 |
1 |
|
|
T1 |
252 |
|
T13 |
10 |
|
T2 |
17160 |
| auto[1] |
auto[1] |
auto[1] |
437988 |
1 |
|
|
T1 |
13 |
|
T2 |
2318 |
|
T3 |
1098 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |