Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8900267 |
1 |
|
|
T20 |
364 |
|
T1 |
669 |
|
T11 |
151 |
| auto[1] |
6780405 |
1 |
|
|
T1 |
545 |
|
T13 |
29 |
|
T2 |
38661 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14796536 |
1 |
|
|
T20 |
364 |
|
T1 |
1200 |
|
T11 |
151 |
| auto[1] |
884136 |
1 |
|
|
T1 |
14 |
|
T13 |
1 |
|
T2 |
4772 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8870237 |
1 |
|
|
T20 |
364 |
|
T1 |
715 |
|
T11 |
151 |
| auto[1] |
6810435 |
1 |
|
|
T1 |
499 |
|
T13 |
45 |
|
T2 |
39893 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2949771 |
1 |
|
|
T1 |
273 |
|
T13 |
25 |
|
T2 |
17482 |
| auto[1] |
auto[0] |
auto[1] |
439261 |
1 |
|
|
T1 |
8 |
|
T13 |
1 |
|
T2 |
2389 |
| auto[1] |
auto[1] |
auto[0] |
2976528 |
1 |
|
|
T1 |
212 |
|
T13 |
19 |
|
T2 |
17639 |
| auto[1] |
auto[1] |
auto[1] |
444875 |
1 |
|
|
T1 |
6 |
|
T2 |
2383 |
|
T3 |
1098 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |