Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8924990 |
1 |
|
|
T20 |
364 |
|
T1 |
614 |
|
T11 |
151 |
| auto[1] |
6755682 |
1 |
|
|
T1 |
600 |
|
T13 |
41 |
|
T2 |
38470 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14803253 |
1 |
|
|
T20 |
364 |
|
T1 |
1192 |
|
T11 |
151 |
| auto[1] |
877419 |
1 |
|
|
T1 |
22 |
|
T13 |
1 |
|
T2 |
4634 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8911466 |
1 |
|
|
T20 |
364 |
|
T1 |
537 |
|
T11 |
151 |
| auto[1] |
6769206 |
1 |
|
|
T1 |
677 |
|
T13 |
46 |
|
T2 |
39343 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2959436 |
1 |
|
|
T1 |
332 |
|
T13 |
25 |
|
T2 |
17829 |
| auto[1] |
auto[0] |
auto[1] |
440472 |
1 |
|
|
T1 |
10 |
|
T13 |
1 |
|
T2 |
2401 |
| auto[1] |
auto[1] |
auto[0] |
2932351 |
1 |
|
|
T1 |
323 |
|
T13 |
20 |
|
T2 |
16880 |
| auto[1] |
auto[1] |
auto[1] |
436947 |
1 |
|
|
T1 |
12 |
|
T2 |
2233 |
|
T3 |
1126 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |