Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8911801 |
1 |
|
|
T20 |
364 |
|
T1 |
598 |
|
T11 |
151 |
| auto[1] |
6768871 |
1 |
|
|
T1 |
616 |
|
T13 |
40 |
|
T2 |
38934 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14802060 |
1 |
|
|
T20 |
364 |
|
T1 |
1179 |
|
T11 |
151 |
| auto[1] |
878612 |
1 |
|
|
T1 |
35 |
|
T2 |
4593 |
|
T3 |
2509 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8895486 |
1 |
|
|
T20 |
364 |
|
T1 |
558 |
|
T11 |
151 |
| auto[1] |
6785186 |
1 |
|
|
T1 |
656 |
|
T13 |
25 |
|
T2 |
39348 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2951104 |
1 |
|
|
T1 |
215 |
|
T13 |
12 |
|
T2 |
17852 |
| auto[1] |
auto[0] |
auto[1] |
439061 |
1 |
|
|
T1 |
15 |
|
T2 |
2377 |
|
T3 |
1324 |
| auto[1] |
auto[1] |
auto[0] |
2955470 |
1 |
|
|
T1 |
406 |
|
T13 |
13 |
|
T2 |
16903 |
| auto[1] |
auto[1] |
auto[1] |
439551 |
1 |
|
|
T1 |
20 |
|
T2 |
2216 |
|
T3 |
1185 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |