Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8894955 |
1 |
|
|
T20 |
364 |
|
T1 |
597 |
|
T11 |
151 |
| auto[1] |
6785717 |
1 |
|
|
T1 |
617 |
|
T13 |
36 |
|
T2 |
39664 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12923529 |
1 |
|
|
T20 |
364 |
|
T1 |
736 |
|
T11 |
151 |
| auto[1] |
2757143 |
1 |
|
|
T1 |
478 |
|
T13 |
16 |
|
T2 |
15624 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8942243 |
1 |
|
|
T20 |
364 |
|
T1 |
583 |
|
T11 |
151 |
| auto[1] |
6738429 |
1 |
|
|
T1 |
631 |
|
T13 |
36 |
|
T2 |
40997 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1988371 |
1 |
|
|
T1 |
87 |
|
T13 |
3 |
|
T2 |
12832 |
| auto[1] |
auto[0] |
auto[1] |
1377004 |
1 |
|
|
T1 |
226 |
|
T13 |
13 |
|
T2 |
7960 |
| auto[1] |
auto[1] |
auto[0] |
1992915 |
1 |
|
|
T1 |
66 |
|
T13 |
17 |
|
T2 |
12541 |
| auto[1] |
auto[1] |
auto[1] |
1380139 |
1 |
|
|
T1 |
252 |
|
T13 |
3 |
|
T2 |
7664 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |