Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8928362 |
1 |
|
|
T20 |
364 |
|
T1 |
613 |
|
T11 |
151 |
| auto[1] |
6752310 |
1 |
|
|
T1 |
601 |
|
T13 |
35 |
|
T2 |
40341 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12919968 |
1 |
|
|
T20 |
364 |
|
T1 |
792 |
|
T11 |
151 |
| auto[1] |
2760704 |
1 |
|
|
T1 |
422 |
|
T13 |
17 |
|
T2 |
14571 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8909633 |
1 |
|
|
T20 |
364 |
|
T1 |
563 |
|
T11 |
151 |
| auto[1] |
6771039 |
1 |
|
|
T1 |
651 |
|
T13 |
26 |
|
T2 |
39473 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2001428 |
1 |
|
|
T1 |
100 |
|
T13 |
4 |
|
T2 |
11759 |
| auto[1] |
auto[0] |
auto[1] |
1380317 |
1 |
|
|
T1 |
234 |
|
T13 |
12 |
|
T2 |
7384 |
| auto[1] |
auto[1] |
auto[0] |
2008907 |
1 |
|
|
T1 |
129 |
|
T13 |
5 |
|
T2 |
13143 |
| auto[1] |
auto[1] |
auto[1] |
1380387 |
1 |
|
|
T1 |
188 |
|
T13 |
5 |
|
T2 |
7187 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |