Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8923401 |
1 |
|
|
T20 |
364 |
|
T1 |
707 |
|
T11 |
151 |
| auto[1] |
6757271 |
1 |
|
|
T1 |
507 |
|
T13 |
28 |
|
T2 |
38351 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12920737 |
1 |
|
|
T20 |
364 |
|
T1 |
720 |
|
T11 |
151 |
| auto[1] |
2759935 |
1 |
|
|
T1 |
494 |
|
T13 |
4 |
|
T2 |
15106 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8925841 |
1 |
|
|
T20 |
364 |
|
T1 |
534 |
|
T11 |
151 |
| auto[1] |
6754831 |
1 |
|
|
T1 |
680 |
|
T13 |
12 |
|
T2 |
40617 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1986935 |
1 |
|
|
T1 |
98 |
|
T13 |
5 |
|
T2 |
12986 |
| auto[1] |
auto[0] |
auto[1] |
1375906 |
1 |
|
|
T1 |
252 |
|
T13 |
1 |
|
T2 |
8123 |
| auto[1] |
auto[1] |
auto[0] |
2007961 |
1 |
|
|
T1 |
88 |
|
T13 |
3 |
|
T2 |
12525 |
| auto[1] |
auto[1] |
auto[1] |
1384029 |
1 |
|
|
T1 |
242 |
|
T13 |
3 |
|
T2 |
6983 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |