Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8935684 |
1 |
|
|
T20 |
364 |
|
T1 |
687 |
|
T11 |
151 |
| auto[1] |
6744988 |
1 |
|
|
T1 |
527 |
|
T13 |
43 |
|
T2 |
39568 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12915055 |
1 |
|
|
T20 |
364 |
|
T1 |
773 |
|
T11 |
151 |
| auto[1] |
2765617 |
1 |
|
|
T1 |
441 |
|
T13 |
17 |
|
T2 |
15212 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8910249 |
1 |
|
|
T20 |
364 |
|
T1 |
645 |
|
T11 |
151 |
| auto[1] |
6770423 |
1 |
|
|
T1 |
569 |
|
T13 |
25 |
|
T2 |
40203 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2014325 |
1 |
|
|
T1 |
91 |
|
T13 |
3 |
|
T2 |
12240 |
| auto[1] |
auto[0] |
auto[1] |
1389696 |
1 |
|
|
T1 |
252 |
|
T13 |
9 |
|
T2 |
7538 |
| auto[1] |
auto[1] |
auto[0] |
1990481 |
1 |
|
|
T1 |
37 |
|
T13 |
5 |
|
T2 |
12751 |
| auto[1] |
auto[1] |
auto[1] |
1375921 |
1 |
|
|
T1 |
189 |
|
T13 |
8 |
|
T2 |
7674 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |