Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14806925 |
1 |
|
|
T20 |
364 |
|
T1 |
1182 |
|
T11 |
151 |
| auto[1] |
873747 |
1 |
|
|
T1 |
32 |
|
T2 |
4636 |
|
T3 |
2326 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8924866 |
1 |
|
|
T20 |
364 |
|
T1 |
571 |
|
T11 |
151 |
| auto[1] |
6755806 |
1 |
|
|
T1 |
643 |
|
T13 |
35 |
|
T2 |
39355 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2950914 |
1 |
|
|
T1 |
356 |
|
T13 |
18 |
|
T2 |
17841 |
| auto[1] |
auto[0] |
auto[1] |
436783 |
1 |
|
|
T1 |
22 |
|
T2 |
2336 |
|
T3 |
1091 |
| auto[1] |
auto[1] |
auto[0] |
2931145 |
1 |
|
|
T1 |
255 |
|
T13 |
17 |
|
T2 |
16878 |
| auto[1] |
auto[1] |
auto[1] |
436964 |
1 |
|
|
T1 |
10 |
|
T2 |
2300 |
|
T3 |
1235 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |