Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8942513 |
1 |
|
|
T20 |
364 |
|
T1 |
600 |
|
T11 |
151 |
| auto[1] |
6738159 |
1 |
|
|
T1 |
614 |
|
T13 |
18 |
|
T2 |
40591 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12916895 |
1 |
|
|
T20 |
364 |
|
T1 |
777 |
|
T11 |
151 |
| auto[1] |
2763777 |
1 |
|
|
T1 |
437 |
|
T13 |
6 |
|
T2 |
14732 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8922653 |
1 |
|
|
T20 |
364 |
|
T1 |
695 |
|
T11 |
151 |
| auto[1] |
6758019 |
1 |
|
|
T1 |
519 |
|
T13 |
13 |
|
T2 |
38891 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2006334 |
1 |
|
|
T1 |
60 |
|
T13 |
7 |
|
T2 |
11411 |
| auto[1] |
auto[0] |
auto[1] |
1389806 |
1 |
|
|
T1 |
165 |
|
T13 |
6 |
|
T2 |
6929 |
| auto[1] |
auto[1] |
auto[0] |
1987908 |
1 |
|
|
T1 |
22 |
|
T2 |
12748 |
|
T3 |
3602 |
| auto[1] |
auto[1] |
auto[1] |
1373971 |
1 |
|
|
T1 |
272 |
|
T2 |
7803 |
|
T3 |
6198 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |