Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8909791 |
1 |
|
|
T20 |
364 |
|
T1 |
626 |
|
T11 |
151 |
| auto[1] |
6770881 |
1 |
|
|
T1 |
588 |
|
T13 |
38 |
|
T2 |
40089 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12924405 |
1 |
|
|
T20 |
364 |
|
T1 |
931 |
|
T11 |
151 |
| auto[1] |
2756267 |
1 |
|
|
T1 |
283 |
|
T13 |
9 |
|
T2 |
13843 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8928817 |
1 |
|
|
T20 |
364 |
|
T1 |
846 |
|
T11 |
151 |
| auto[1] |
6751855 |
1 |
|
|
T1 |
368 |
|
T13 |
17 |
|
T2 |
37755 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1997540 |
1 |
|
|
T1 |
29 |
|
T13 |
1 |
|
T2 |
11678 |
| auto[1] |
auto[0] |
auto[1] |
1379921 |
1 |
|
|
T1 |
156 |
|
T13 |
5 |
|
T2 |
6807 |
| auto[1] |
auto[1] |
auto[0] |
1998048 |
1 |
|
|
T1 |
56 |
|
T13 |
7 |
|
T2 |
12234 |
| auto[1] |
auto[1] |
auto[1] |
1376346 |
1 |
|
|
T1 |
127 |
|
T13 |
4 |
|
T2 |
7036 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |