Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8903902 |
1 |
|
|
T20 |
364 |
|
T1 |
717 |
|
T11 |
151 |
| auto[1] |
6776770 |
1 |
|
|
T1 |
497 |
|
T13 |
9 |
|
T2 |
37495 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12926758 |
1 |
|
|
T20 |
364 |
|
T1 |
814 |
|
T11 |
151 |
| auto[1] |
2753914 |
1 |
|
|
T1 |
400 |
|
T13 |
13 |
|
T2 |
14791 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8933928 |
1 |
|
|
T20 |
364 |
|
T1 |
616 |
|
T11 |
151 |
| auto[1] |
6746744 |
1 |
|
|
T1 |
598 |
|
T13 |
34 |
|
T2 |
40288 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1982464 |
1 |
|
|
T1 |
95 |
|
T13 |
21 |
|
T2 |
13615 |
| auto[1] |
auto[0] |
auto[1] |
1371778 |
1 |
|
|
T1 |
230 |
|
T13 |
8 |
|
T2 |
7831 |
| auto[1] |
auto[1] |
auto[0] |
2010366 |
1 |
|
|
T1 |
103 |
|
T2 |
11882 |
|
T3 |
3393 |
| auto[1] |
auto[1] |
auto[1] |
1382136 |
1 |
|
|
T1 |
170 |
|
T13 |
5 |
|
T2 |
6960 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |