Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8947790 |
1 |
|
|
T20 |
364 |
|
T1 |
832 |
|
T11 |
151 |
| auto[1] |
6732882 |
1 |
|
|
T1 |
382 |
|
T13 |
27 |
|
T2 |
38627 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12930026 |
1 |
|
|
T20 |
364 |
|
T1 |
754 |
|
T11 |
151 |
| auto[1] |
2750646 |
1 |
|
|
T1 |
460 |
|
T13 |
7 |
|
T2 |
14510 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8963259 |
1 |
|
|
T20 |
364 |
|
T1 |
591 |
|
T11 |
151 |
| auto[1] |
6717413 |
1 |
|
|
T1 |
623 |
|
T13 |
29 |
|
T2 |
39372 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1988362 |
1 |
|
|
T1 |
134 |
|
T13 |
18 |
|
T2 |
13187 |
| auto[1] |
auto[0] |
auto[1] |
1379238 |
1 |
|
|
T1 |
336 |
|
T13 |
5 |
|
T2 |
7558 |
| auto[1] |
auto[1] |
auto[0] |
1978405 |
1 |
|
|
T1 |
29 |
|
T13 |
4 |
|
T2 |
11675 |
| auto[1] |
auto[1] |
auto[1] |
1371408 |
1 |
|
|
T1 |
124 |
|
T13 |
2 |
|
T2 |
6952 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |