Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8932271 |
1 |
|
|
T20 |
364 |
|
T1 |
527 |
|
T11 |
151 |
| auto[1] |
6748401 |
1 |
|
|
T1 |
687 |
|
T13 |
52 |
|
T2 |
39613 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12928322 |
1 |
|
|
T20 |
364 |
|
T1 |
713 |
|
T11 |
151 |
| auto[1] |
2752350 |
1 |
|
|
T1 |
501 |
|
T13 |
30 |
|
T2 |
14127 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8947120 |
1 |
|
|
T20 |
364 |
|
T1 |
614 |
|
T11 |
151 |
| auto[1] |
6733552 |
1 |
|
|
T1 |
600 |
|
T13 |
39 |
|
T2 |
37663 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1986840 |
1 |
|
|
T1 |
45 |
|
T13 |
6 |
|
T2 |
11454 |
| auto[1] |
auto[0] |
auto[1] |
1379373 |
1 |
|
|
T1 |
247 |
|
T13 |
4 |
|
T2 |
6760 |
| auto[1] |
auto[1] |
auto[0] |
1994362 |
1 |
|
|
T1 |
54 |
|
T13 |
3 |
|
T2 |
12082 |
| auto[1] |
auto[1] |
auto[1] |
1372977 |
1 |
|
|
T1 |
254 |
|
T13 |
26 |
|
T2 |
7367 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |