Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8944098 |
1 |
|
|
T20 |
364 |
|
T1 |
510 |
|
T11 |
151 |
| auto[1] |
6736574 |
1 |
|
|
T1 |
704 |
|
T13 |
28 |
|
T2 |
40150 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12912938 |
1 |
|
|
T20 |
364 |
|
T1 |
672 |
|
T11 |
151 |
| auto[1] |
2767734 |
1 |
|
|
T1 |
542 |
|
T13 |
40 |
|
T2 |
14247 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8907545 |
1 |
|
|
T20 |
364 |
|
T1 |
561 |
|
T11 |
151 |
| auto[1] |
6773127 |
1 |
|
|
T1 |
653 |
|
T13 |
53 |
|
T2 |
38461 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2001670 |
1 |
|
|
T1 |
42 |
|
T13 |
3 |
|
T2 |
11950 |
| auto[1] |
auto[0] |
auto[1] |
1384401 |
1 |
|
|
T1 |
190 |
|
T13 |
34 |
|
T2 |
7007 |
| auto[1] |
auto[1] |
auto[0] |
2003723 |
1 |
|
|
T1 |
69 |
|
T13 |
10 |
|
T2 |
12264 |
| auto[1] |
auto[1] |
auto[1] |
1383333 |
1 |
|
|
T1 |
352 |
|
T13 |
6 |
|
T2 |
7240 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |