Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8894992 |
1 |
|
|
T20 |
364 |
|
T1 |
638 |
|
T11 |
151 |
| auto[1] |
6785680 |
1 |
|
|
T1 |
576 |
|
T13 |
14 |
|
T2 |
40376 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12924844 |
1 |
|
|
T20 |
364 |
|
T1 |
748 |
|
T11 |
151 |
| auto[1] |
2755828 |
1 |
|
|
T1 |
466 |
|
T13 |
26 |
|
T2 |
14432 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8933981 |
1 |
|
|
T20 |
364 |
|
T1 |
544 |
|
T11 |
151 |
| auto[1] |
6746691 |
1 |
|
|
T1 |
670 |
|
T13 |
41 |
|
T2 |
39104 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1991462 |
1 |
|
|
T1 |
127 |
|
T13 |
15 |
|
T2 |
12075 |
| auto[1] |
auto[0] |
auto[1] |
1372730 |
1 |
|
|
T1 |
214 |
|
T13 |
22 |
|
T2 |
6888 |
| auto[1] |
auto[1] |
auto[0] |
1999401 |
1 |
|
|
T1 |
77 |
|
T2 |
12597 |
|
T3 |
3752 |
| auto[1] |
auto[1] |
auto[1] |
1383098 |
1 |
|
|
T1 |
252 |
|
T13 |
4 |
|
T2 |
7544 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |