Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8931892 |
1 |
|
|
T20 |
364 |
|
T1 |
550 |
|
T11 |
151 |
| auto[1] |
6748780 |
1 |
|
|
T1 |
664 |
|
T13 |
10 |
|
T2 |
41104 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12925311 |
1 |
|
|
T20 |
364 |
|
T1 |
786 |
|
T11 |
151 |
| auto[1] |
2755361 |
1 |
|
|
T1 |
428 |
|
T13 |
10 |
|
T2 |
14291 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8928132 |
1 |
|
|
T20 |
364 |
|
T1 |
624 |
|
T11 |
151 |
| auto[1] |
6752540 |
1 |
|
|
T1 |
590 |
|
T13 |
20 |
|
T2 |
38603 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2016187 |
1 |
|
|
T1 |
79 |
|
T13 |
9 |
|
T2 |
11773 |
| auto[1] |
auto[0] |
auto[1] |
1381425 |
1 |
|
|
T1 |
176 |
|
T13 |
8 |
|
T2 |
6870 |
| auto[1] |
auto[1] |
auto[0] |
1980992 |
1 |
|
|
T1 |
83 |
|
T13 |
1 |
|
T2 |
12539 |
| auto[1] |
auto[1] |
auto[1] |
1373936 |
1 |
|
|
T1 |
252 |
|
T13 |
2 |
|
T2 |
7421 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |