Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8939583 |
1 |
|
|
T20 |
364 |
|
T1 |
565 |
|
T11 |
151 |
| auto[1] |
6741089 |
1 |
|
|
T1 |
649 |
|
T13 |
27 |
|
T2 |
39619 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12909168 |
1 |
|
|
T20 |
364 |
|
T1 |
727 |
|
T11 |
151 |
| auto[1] |
2771504 |
1 |
|
|
T1 |
487 |
|
T13 |
3 |
|
T2 |
14723 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8876444 |
1 |
|
|
T20 |
364 |
|
T1 |
612 |
|
T11 |
151 |
| auto[1] |
6804228 |
1 |
|
|
T1 |
602 |
|
T13 |
36 |
|
T2 |
39599 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2023061 |
1 |
|
|
T1 |
31 |
|
T13 |
26 |
|
T2 |
12143 |
| auto[1] |
auto[0] |
auto[1] |
1390021 |
1 |
|
|
T1 |
238 |
|
T13 |
3 |
|
T2 |
7138 |
| auto[1] |
auto[1] |
auto[0] |
2009663 |
1 |
|
|
T1 |
84 |
|
T13 |
7 |
|
T2 |
12733 |
| auto[1] |
auto[1] |
auto[1] |
1381483 |
1 |
|
|
T1 |
249 |
|
T2 |
7585 |
|
T3 |
7038 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |