Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8932644 |
1 |
|
|
T20 |
364 |
|
T1 |
644 |
|
T11 |
151 |
| auto[1] |
6748028 |
1 |
|
|
T1 |
570 |
|
T13 |
33 |
|
T2 |
40684 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14804672 |
1 |
|
|
T20 |
364 |
|
T1 |
1196 |
|
T11 |
151 |
| auto[1] |
876000 |
1 |
|
|
T1 |
18 |
|
T13 |
1 |
|
T2 |
4891 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8910521 |
1 |
|
|
T20 |
364 |
|
T1 |
646 |
|
T11 |
151 |
| auto[1] |
6770151 |
1 |
|
|
T1 |
568 |
|
T13 |
15 |
|
T2 |
40194 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2948723 |
1 |
|
|
T1 |
306 |
|
T13 |
9 |
|
T2 |
17297 |
| auto[1] |
auto[0] |
auto[1] |
438961 |
1 |
|
|
T1 |
11 |
|
T13 |
1 |
|
T2 |
2380 |
| auto[1] |
auto[1] |
auto[0] |
2945428 |
1 |
|
|
T1 |
244 |
|
T13 |
5 |
|
T2 |
18006 |
| auto[1] |
auto[1] |
auto[1] |
437039 |
1 |
|
|
T1 |
7 |
|
T2 |
2511 |
|
T3 |
1073 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |