Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8921216 |
1 |
|
|
T20 |
364 |
|
T1 |
507 |
|
T11 |
151 |
| auto[1] |
6759456 |
1 |
|
|
T1 |
707 |
|
T13 |
25 |
|
T2 |
38792 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12918770 |
1 |
|
|
T20 |
364 |
|
T1 |
505 |
|
T11 |
151 |
| auto[1] |
2761902 |
1 |
|
|
T1 |
709 |
|
T13 |
8 |
|
T2 |
14766 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8922395 |
1 |
|
|
T20 |
364 |
|
T1 |
344 |
|
T11 |
151 |
| auto[1] |
6758277 |
1 |
|
|
T1 |
870 |
|
T13 |
19 |
|
T2 |
38734 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1990860 |
1 |
|
|
T1 |
45 |
|
T13 |
6 |
|
T2 |
11916 |
| auto[1] |
auto[0] |
auto[1] |
1381570 |
1 |
|
|
T1 |
324 |
|
T13 |
6 |
|
T2 |
7595 |
| auto[1] |
auto[1] |
auto[0] |
2005515 |
1 |
|
|
T1 |
116 |
|
T13 |
5 |
|
T2 |
12052 |
| auto[1] |
auto[1] |
auto[1] |
1380332 |
1 |
|
|
T1 |
385 |
|
T13 |
2 |
|
T2 |
7171 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |