Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8945111 |
1 |
|
|
T20 |
364 |
|
T1 |
342 |
|
T11 |
151 |
| auto[1] |
6735561 |
1 |
|
|
T1 |
872 |
|
T13 |
9 |
|
T2 |
38868 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12928702 |
1 |
|
|
T20 |
364 |
|
T1 |
641 |
|
T11 |
151 |
| auto[1] |
2751970 |
1 |
|
|
T1 |
573 |
|
T13 |
8 |
|
T2 |
14595 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8944452 |
1 |
|
|
T20 |
364 |
|
T1 |
480 |
|
T11 |
151 |
| auto[1] |
6736220 |
1 |
|
|
T1 |
734 |
|
T13 |
39 |
|
T2 |
38491 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2000236 |
1 |
|
|
T1 |
58 |
|
T13 |
26 |
|
T2 |
11879 |
| auto[1] |
auto[0] |
auto[1] |
1382111 |
1 |
|
|
T1 |
161 |
|
T13 |
5 |
|
T2 |
7153 |
| auto[1] |
auto[1] |
auto[0] |
1984014 |
1 |
|
|
T1 |
103 |
|
T13 |
5 |
|
T2 |
12017 |
| auto[1] |
auto[1] |
auto[1] |
1369859 |
1 |
|
|
T1 |
412 |
|
T13 |
3 |
|
T2 |
7442 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |