Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8908300 |
1 |
|
|
T20 |
364 |
|
T1 |
598 |
|
T11 |
151 |
| auto[1] |
6772372 |
1 |
|
|
T1 |
616 |
|
T13 |
27 |
|
T2 |
37651 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12907758 |
1 |
|
|
T20 |
364 |
|
T1 |
741 |
|
T11 |
151 |
| auto[1] |
2772914 |
1 |
|
|
T1 |
473 |
|
T13 |
24 |
|
T2 |
13995 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8889782 |
1 |
|
|
T20 |
364 |
|
T1 |
609 |
|
T11 |
151 |
| auto[1] |
6790890 |
1 |
|
|
T1 |
605 |
|
T13 |
33 |
|
T2 |
38029 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2007350 |
1 |
|
|
T1 |
51 |
|
T13 |
3 |
|
T2 |
12370 |
| auto[1] |
auto[0] |
auto[1] |
1383844 |
1 |
|
|
T1 |
253 |
|
T13 |
23 |
|
T2 |
7225 |
| auto[1] |
auto[1] |
auto[0] |
2010626 |
1 |
|
|
T1 |
81 |
|
T13 |
6 |
|
T2 |
11664 |
| auto[1] |
auto[1] |
auto[1] |
1389070 |
1 |
|
|
T1 |
220 |
|
T13 |
1 |
|
T2 |
6770 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |