Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8970422 |
1 |
|
|
T20 |
364 |
|
T1 |
736 |
|
T11 |
151 |
| auto[1] |
6710250 |
1 |
|
|
T1 |
478 |
|
T13 |
36 |
|
T2 |
39465 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14811717 |
1 |
|
|
T20 |
364 |
|
T1 |
1191 |
|
T11 |
151 |
| auto[1] |
868955 |
1 |
|
|
T1 |
23 |
|
T2 |
4533 |
|
T3 |
2101 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8956359 |
1 |
|
|
T20 |
364 |
|
T1 |
677 |
|
T11 |
151 |
| auto[1] |
6724313 |
1 |
|
|
T1 |
537 |
|
T13 |
36 |
|
T2 |
38033 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2947605 |
1 |
|
|
T1 |
309 |
|
T13 |
27 |
|
T2 |
16549 |
| auto[1] |
auto[0] |
auto[1] |
437657 |
1 |
|
|
T1 |
11 |
|
T2 |
2156 |
|
T3 |
1098 |
| auto[1] |
auto[1] |
auto[0] |
2907753 |
1 |
|
|
T1 |
205 |
|
T13 |
9 |
|
T2 |
16951 |
| auto[1] |
auto[1] |
auto[1] |
431298 |
1 |
|
|
T1 |
12 |
|
T2 |
2377 |
|
T3 |
1003 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |