Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8928223 |
1 |
|
|
T20 |
364 |
|
T1 |
372 |
|
T11 |
151 |
| auto[1] |
6752449 |
1 |
|
|
T1 |
842 |
|
T13 |
23 |
|
T2 |
39190 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14808084 |
1 |
|
|
T20 |
364 |
|
T1 |
1186 |
|
T11 |
151 |
| auto[1] |
872588 |
1 |
|
|
T1 |
28 |
|
T2 |
4572 |
|
T3 |
2252 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8947322 |
1 |
|
|
T20 |
364 |
|
T1 |
579 |
|
T11 |
151 |
| auto[1] |
6733350 |
1 |
|
|
T1 |
635 |
|
T13 |
16 |
|
T2 |
38895 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2920384 |
1 |
|
|
T1 |
186 |
|
T13 |
16 |
|
T2 |
17467 |
| auto[1] |
auto[0] |
auto[1] |
433333 |
1 |
|
|
T1 |
9 |
|
T2 |
2376 |
|
T3 |
1127 |
| auto[1] |
auto[1] |
auto[0] |
2940378 |
1 |
|
|
T1 |
421 |
|
T2 |
16856 |
|
T3 |
9292 |
| auto[1] |
auto[1] |
auto[1] |
439255 |
1 |
|
|
T1 |
19 |
|
T2 |
2196 |
|
T3 |
1125 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |