Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8917572 |
1 |
|
|
T20 |
364 |
|
T1 |
640 |
|
T11 |
151 |
| auto[1] |
6763100 |
1 |
|
|
T1 |
574 |
|
T13 |
31 |
|
T2 |
38738 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14806862 |
1 |
|
|
T20 |
364 |
|
T1 |
1195 |
|
T11 |
151 |
| auto[1] |
873810 |
1 |
|
|
T1 |
19 |
|
T13 |
1 |
|
T2 |
4740 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8931968 |
1 |
|
|
T20 |
364 |
|
T1 |
571 |
|
T11 |
151 |
| auto[1] |
6748704 |
1 |
|
|
T1 |
643 |
|
T13 |
35 |
|
T2 |
40011 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2942862 |
1 |
|
|
T1 |
324 |
|
T13 |
19 |
|
T2 |
17623 |
| auto[1] |
auto[0] |
auto[1] |
437173 |
1 |
|
|
T1 |
14 |
|
T2 |
2374 |
|
T3 |
1173 |
| auto[1] |
auto[1] |
auto[0] |
2932032 |
1 |
|
|
T1 |
300 |
|
T13 |
15 |
|
T2 |
17648 |
| auto[1] |
auto[1] |
auto[1] |
436637 |
1 |
|
|
T1 |
5 |
|
T13 |
1 |
|
T2 |
2366 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |