Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8902403 |
1 |
|
|
T20 |
364 |
|
T1 |
650 |
|
T11 |
151 |
| auto[1] |
6778269 |
1 |
|
|
T1 |
564 |
|
T13 |
36 |
|
T2 |
38678 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14805180 |
1 |
|
|
T20 |
364 |
|
T1 |
1187 |
|
T11 |
151 |
| auto[1] |
875492 |
1 |
|
|
T1 |
27 |
|
T2 |
4585 |
|
T3 |
2266 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8921299 |
1 |
|
|
T20 |
364 |
|
T1 |
590 |
|
T11 |
151 |
| auto[1] |
6759373 |
1 |
|
|
T1 |
624 |
|
T13 |
38 |
|
T2 |
39075 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2934241 |
1 |
|
|
T1 |
345 |
|
T13 |
26 |
|
T2 |
17356 |
| auto[1] |
auto[0] |
auto[1] |
435956 |
1 |
|
|
T1 |
17 |
|
T2 |
2277 |
|
T3 |
1185 |
| auto[1] |
auto[1] |
auto[0] |
2949640 |
1 |
|
|
T1 |
252 |
|
T13 |
12 |
|
T2 |
17134 |
| auto[1] |
auto[1] |
auto[1] |
439536 |
1 |
|
|
T1 |
10 |
|
T2 |
2308 |
|
T3 |
1081 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |