Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8902136 |
1 |
|
|
T20 |
364 |
|
T1 |
497 |
|
T11 |
151 |
| auto[1] |
6778536 |
1 |
|
|
T1 |
717 |
|
T13 |
44 |
|
T2 |
39190 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14803600 |
1 |
|
|
T20 |
364 |
|
T1 |
1185 |
|
T11 |
151 |
| auto[1] |
877072 |
1 |
|
|
T1 |
29 |
|
T13 |
1 |
|
T2 |
4725 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8921509 |
1 |
|
|
T20 |
364 |
|
T1 |
556 |
|
T11 |
151 |
| auto[1] |
6759163 |
1 |
|
|
T1 |
658 |
|
T13 |
52 |
|
T2 |
39060 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2930650 |
1 |
|
|
T1 |
254 |
|
T13 |
19 |
|
T2 |
18327 |
| auto[1] |
auto[0] |
auto[1] |
436639 |
1 |
|
|
T1 |
7 |
|
T2 |
2600 |
|
T3 |
1041 |
| auto[1] |
auto[1] |
auto[0] |
2951441 |
1 |
|
|
T1 |
375 |
|
T13 |
32 |
|
T2 |
16008 |
| auto[1] |
auto[1] |
auto[1] |
440433 |
1 |
|
|
T1 |
22 |
|
T13 |
1 |
|
T2 |
2125 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |