Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3753176	1			T31	1		T32	36		T33	192852
all_pins[1]	3753176	1			T31	1		T32	36		T33	192852
all_pins[2]	3753176	1			T31	1		T32	36		T33	192852
all_pins[3]	3753176	1			T31	1		T32	36		T33	192852
all_pins[4]	3753176	1			T31	1		T32	36		T33	192852
all_pins[5]	3753176	1			T31	1		T32	36		T33	192852
all_pins[6]	3753176	1			T31	1		T32	36		T33	192852
all_pins[7]	3753176	1			T31	1		T32	36		T33	192852
all_pins[8]	3753176	1			T31	1		T32	36		T33	192852
all_pins[9]	3753176	1			T31	1		T32	36		T33	192852
all_pins[10]	3753176	1			T31	1		T32	36		T33	192852
all_pins[11]	3753176	1			T31	1		T32	36		T33	192852
all_pins[12]	3753176	1			T31	1		T32	36		T33	192852
all_pins[13]	3753176	1			T31	1		T32	36		T33	192852
all_pins[14]	3753176	1			T31	1		T32	36		T33	192852
all_pins[15]	3753176	1			T31	1		T32	36		T33	192852
all_pins[16]	3753176	1			T31	1		T32	36		T33	192852
all_pins[17]	3753176	1			T31	1		T32	36		T33	192852
all_pins[18]	3753176	1			T31	1		T32	36		T33	192852
all_pins[19]	3753176	1			T31	1		T32	36		T33	192852
all_pins[20]	3753176	1			T31	1		T32	36		T33	192852
all_pins[21]	3753176	1			T31	1		T32	36		T33	192852
all_pins[22]	3753176	1			T31	1		T32	36		T33	192852
all_pins[23]	3753176	1			T31	1		T32	36		T33	192852
all_pins[24]	3753176	1			T31	1		T32	36		T33	192852
all_pins[25]	3753176	1			T31	1		T32	36		T33	192852
all_pins[26]	3753176	1			T31	1		T32	36		T33	192852
all_pins[27]	3753176	1			T31	1		T32	36		T33	192852
all_pins[28]	3753176	1			T31	1		T32	36		T33	192852
all_pins[29]	3753176	1			T31	1		T32	36		T33	192852
all_pins[30]	3753176	1			T31	1		T32	36		T33	192852
all_pins[31]	3753176	1			T31	1		T32	36		T33	192852

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	74619909	1			T31	32		T32	591		T33	383266
values[0x1]	45481723	1			T32	561		T33	233859		T19	362
transitions[0x0=>0x1]	27262673	1			T32	279		T33	140134		T19	279
transitions[0x1=>0x0]	27262514	1			T32	278		T33	140134		T19	279

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2332657	1			T31	1		T32	12		T33	120671
all_pins[0]	values[0x1]	1420519	1			T32	24		T33	72181		T19	10
all_pins[0]	transitions[0x0=>0x1]	881691	1			T32	10		T33	44625		T19	10
all_pins[0]	transitions[0x1=>0x0]	875946	1			T32	6		T33	45345		T19	20
all_pins[1]	values[0x0]	2329475	1			T31	1		T32	12		T33	119550
all_pins[1]	values[0x1]	1423701	1			T32	24		T33	73302		T19	9
all_pins[1]	transitions[0x0=>0x1]	850770	1			T32	8		T33	43877		T19	5
all_pins[1]	transitions[0x1=>0x0]	847588	1			T32	8		T33	42756		T19	6
all_pins[2]	values[0x0]	2333656	1			T31	1		T32	17		T33	119262
all_pins[2]	values[0x1]	1419520	1			T32	19		T33	73590		T19	19
all_pins[2]	transitions[0x0=>0x1]	849612	1			T32	8		T33	43786		T19	12
all_pins[2]	transitions[0x1=>0x0]	853793	1			T32	13		T33	43498		T19	2
all_pins[3]	values[0x0]	2330117	1			T31	1		T32	21		T33	119299
all_pins[3]	values[0x1]	1423059	1			T32	15		T33	73553		T19	9
all_pins[3]	transitions[0x0=>0x1]	854496	1			T32	7		T33	44058		T19	5
all_pins[3]	transitions[0x1=>0x0]	850957	1			T32	11		T33	44095		T19	15
all_pins[4]	values[0x0]	2330081	1			T31	1		T32	20		T33	118825
all_pins[4]	values[0x1]	1423095	1			T32	16		T33	74027		T19	1
all_pins[4]	transitions[0x0=>0x1]	853019	1			T32	9		T33	44100		T19	1
all_pins[4]	transitions[0x1=>0x0]	852983	1			T32	8		T33	43626		T19	9
all_pins[5]	values[0x0]	2332595	1			T31	1		T32	19		T33	119703
all_pins[5]	values[0x1]	1420581	1			T32	17		T33	73149		T19	5
all_pins[5]	transitions[0x0=>0x1]	849993	1			T32	10		T33	43283		T19	5
all_pins[5]	transitions[0x1=>0x0]	852507	1			T32	9		T33	44161		T19	1
all_pins[6]	values[0x0]	2333614	1			T31	1		T32	21		T33	120300
all_pins[6]	values[0x1]	1419562	1			T32	15		T33	72552		T19	19
all_pins[6]	transitions[0x0=>0x1]	851049	1			T32	11		T33	43396		T19	19
all_pins[6]	transitions[0x1=>0x0]	852068	1			T32	13		T33	43993		T19	5
all_pins[7]	values[0x0]	2327101	1			T31	1		T32	20		T33	120417
all_pins[7]	values[0x1]	1426075	1			T32	16		T33	72435		T19	4
all_pins[7]	transitions[0x0=>0x1]	855923	1			T32	8		T33	43624		T19	3
all_pins[7]	transitions[0x1=>0x0]	849410	1			T32	7		T33	43741		T19	18
all_pins[8]	values[0x0]	2332111	1			T31	1		T32	16		T33	120036
all_pins[8]	values[0x1]	1421065	1			T32	20		T33	72816		T19	14
all_pins[8]	transitions[0x0=>0x1]	850319	1			T32	8		T33	43656		T19	11
all_pins[8]	transitions[0x1=>0x0]	855329	1			T32	4		T33	43275		T19	1
all_pins[9]	values[0x0]	2331185	1			T31	1		T32	19		T33	119998
all_pins[9]	values[0x1]	1421991	1			T32	17		T33	72854		T19	4
all_pins[9]	transitions[0x0=>0x1]	852354	1			T32	10		T33	43997		T19	4
all_pins[9]	transitions[0x1=>0x0]	851428	1			T32	13		T33	43959		T19	14
all_pins[10]	values[0x0]	2331550	1			T31	1		T32	18		T33	119494
all_pins[10]	values[0x1]	1421626	1			T32	18		T33	73358		T19	13
all_pins[10]	transitions[0x0=>0x1]	852503	1			T32	9		T33	43872		T19	13
all_pins[10]	transitions[0x1=>0x0]	852868	1			T32	8		T33	43368		T19	4
all_pins[11]	values[0x0]	2333164	1			T31	1		T32	20		T33	118877
all_pins[11]	values[0x1]	1420012	1			T32	16		T33	73975		T19	12
all_pins[11]	transitions[0x0=>0x1]	849269	1			T32	8		T33	44216		T19	4
all_pins[11]	transitions[0x1=>0x0]	850883	1			T32	10		T33	43599		T19	5
all_pins[12]	values[0x0]	2331313	1			T31	1		T32	28		T33	120132
all_pins[12]	values[0x1]	1421863	1			T32	8		T33	72720		T19	19
all_pins[12]	transitions[0x0=>0x1]	850909	1			T32	3		T33	42955		T19	11
all_pins[12]	transitions[0x1=>0x0]	849058	1			T32	11		T33	44210		T19	4
all_pins[13]	values[0x0]	2325803	1			T31	1		T32	18		T33	119615
all_pins[13]	values[0x1]	1427373	1			T32	18		T33	73237		T19	19
all_pins[13]	transitions[0x0=>0x1]	853031	1			T32	13		T33	43992		T19	13
all_pins[13]	transitions[0x1=>0x0]	847521	1			T32	3		T33	43475		T19	13
all_pins[14]	values[0x0]	2333012	1			T31	1		T32	15		T33	120616
all_pins[14]	values[0x1]	1420164	1			T32	21		T33	72236		T19	16
all_pins[14]	transitions[0x0=>0x1]	847841	1			T32	7		T33	42792		T19	6
all_pins[14]	transitions[0x1=>0x0]	855050	1			T32	4		T33	43793		T19	9
all_pins[15]	values[0x0]	2334227	1			T31	1		T32	19		T33	119717
all_pins[15]	values[0x1]	1418949	1			T32	17		T33	73135		T19	4
all_pins[15]	transitions[0x0=>0x1]	848763	1			T32	7		T33	43923		T19	4
all_pins[15]	transitions[0x1=>0x0]	849978	1			T32	11		T33	43024		T19	16
all_pins[16]	values[0x0]	2334698	1			T31	1		T32	19		T33	119695
all_pins[16]	values[0x1]	1418478	1			T32	17		T33	73157		T19	19
all_pins[16]	transitions[0x0=>0x1]	850790	1			T32	10		T33	44186		T19	16
all_pins[16]	transitions[0x1=>0x0]	851261	1			T32	10		T33	44164		T19	1
all_pins[17]	values[0x0]	2330427	1			T31	1		T32	17		T33	120739
all_pins[17]	values[0x1]	1422749	1			T32	19		T33	72113		T1	10
all_pins[17]	transitions[0x0=>0x1]	853102	1			T32	11		T33	43103		T1	6
all_pins[17]	transitions[0x1=>0x0]	848831	1			T32	9		T33	44147		T19	19
all_pins[18]	values[0x0]	2331035	1			T31	1		T32	15		T33	119116
all_pins[18]	values[0x1]	1422141	1			T32	21		T33	73736		T19	7
all_pins[18]	transitions[0x0=>0x1]	853155	1			T32	8		T33	44327		T19	7
all_pins[18]	transitions[0x1=>0x0]	853763	1			T32	6		T33	42704		T1	5
all_pins[19]	values[0x0]	2332643	1			T31	1		T32	16		T33	119568
all_pins[19]	values[0x1]	1420533	1			T32	20		T33	73284		T19	5
all_pins[19]	transitions[0x0=>0x1]	851062	1			T32	6		T33	43762		T19	3
all_pins[19]	transitions[0x1=>0x0]	852670	1			T32	7		T33	44214		T19	5
all_pins[20]	values[0x0]	2330469	1			T31	1		T32	20		T33	118334
all_pins[20]	values[0x1]	1422707	1			T32	16		T33	74518		T19	12
all_pins[20]	transitions[0x0=>0x1]	851134	1			T32	8		T33	44913		T19	11
all_pins[20]	transitions[0x1=>0x0]	848960	1			T32	12		T33	43679		T19	4
all_pins[21]	values[0x0]	2336361	1			T31	1		T32	16		T33	120629
all_pins[21]	values[0x1]	1416815	1			T32	20		T33	72223		T19	15
all_pins[21]	transitions[0x0=>0x1]	846840	1			T32	12		T33	42378		T19	15
all_pins[21]	transitions[0x1=>0x0]	852732	1			T32	8		T33	44673		T19	12
all_pins[22]	values[0x0]	2332730	1			T31	1		T32	22		T33	120201
all_pins[22]	values[0x1]	1420446	1			T32	14		T33	72651		T19	5
all_pins[22]	transitions[0x0=>0x1]	852900	1			T32	7		T33	43889		T19	5
all_pins[22]	transitions[0x1=>0x0]	849269	1			T32	13		T33	43461		T19	15
all_pins[23]	values[0x0]	2329950	1			T31	1		T32	16		T33	119311
all_pins[23]	values[0x1]	1423226	1			T32	20		T33	73541		T19	22
all_pins[23]	transitions[0x0=>0x1]	852847	1			T32	10		T33	44443		T19	19
all_pins[23]	transitions[0x1=>0x0]	850067	1			T32	4		T33	43553		T19	2
all_pins[24]	values[0x0]	2329032	1			T31	1		T32	17		T33	119472
all_pins[24]	values[0x1]	1424144	1			T32	19		T33	73380		T19	5
all_pins[24]	transitions[0x0=>0x1]	851865	1			T32	7		T33	43980		T19	2
all_pins[24]	transitions[0x1=>0x0]	850947	1			T32	8		T33	44141		T19	19
all_pins[25]	values[0x0]	2330655	1			T31	1		T32	20		T33	119719
all_pins[25]	values[0x1]	1422521	1			T32	16		T33	73133		T19	8
all_pins[25]	transitions[0x0=>0x1]	850581	1			T32	9		T33	43678		T19	8
all_pins[25]	transitions[0x1=>0x0]	852204	1			T32	12		T33	43925		T19	5
all_pins[26]	values[0x0]	2336505	1			T31	1		T32	21		T33	121031
all_pins[26]	values[0x1]	1416671	1			T32	15		T33	71821		T19	26
all_pins[26]	transitions[0x0=>0x1]	847420	1			T32	7		T33	43301		T19	23
all_pins[26]	transitions[0x1=>0x0]	853270	1			T32	8		T33	44613		T19	5
all_pins[27]	values[0x0]	2329216	1			T31	1		T32	23		T33	119316
all_pins[27]	values[0x1]	1423960	1			T32	13		T33	73536		T19	5
all_pins[27]	transitions[0x0=>0x1]	853311	1			T32	5		T33	44477		T1	18
all_pins[27]	transitions[0x1=>0x0]	846022	1			T32	7		T33	42762		T19	21
all_pins[28]	values[0x0]	2333319	1			T31	1		T32	16		T33	120010
all_pins[28]	values[0x1]	1419857	1			T32	20		T33	72842		T19	11
all_pins[28]	transitions[0x0=>0x1]	848988	1			T32	14		T33	43453		T19	7
all_pins[28]	transitions[0x1=>0x0]	853091	1			T32	7		T33	44147		T19	1
all_pins[29]	values[0x0]	2331774	1			T31	1		T32	26		T33	119438
all_pins[29]	values[0x1]	1421402	1			T32	10		T33	73414		T19	18
all_pins[29]	transitions[0x0=>0x1]	851264	1			T32	7		T33	44254		T19	16
all_pins[29]	transitions[0x1=>0x0]	849719	1			T32	17		T33	43682		T19	9
all_pins[30]	values[0x0]	2331191	1			T31	1		T32	17		T33	119624
all_pins[30]	values[0x1]	1421985	1			T32	19		T33	73228		T19	7
all_pins[30]	transitions[0x0=>0x1]	849001	1			T32	13		T33	43795		T19	2
all_pins[30]	transitions[0x1=>0x0]	848418	1			T32	4		T33	43981		T19	13
all_pins[31]	values[0x0]	2338243	1			T31	1		T32	15		T33	119951
all_pins[31]	values[0x1]	1414933	1			T32	21		T33	72901		T19	20
all_pins[31]	transitions[0x0=>0x1]	846871	1			T32	9		T33	43249		T19	19
all_pins[31]	transitions[0x1=>0x0]	853923	1			T32	7		T33	43576		T19	6