Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	12797435	1			T31	324		T32	15907		T33	558903
all_values[1]	12797435	1			T31	324		T32	15907		T33	558903
all_values[2]	12797435	1			T31	324		T32	15907		T33	558903
all_values[3]	12797435	1			T31	324		T32	15907		T33	558903
all_values[4]	12797435	1			T31	324		T32	15907		T33	558903
all_values[5]	12797435	1			T31	324		T32	15907		T33	558903
all_values[6]	12797435	1			T31	324		T32	15907		T33	558903
all_values[7]	12797435	1			T31	324		T32	15907		T33	558903
all_values[8]	12797435	1			T31	324		T32	15907		T33	558903
all_values[9]	12797435	1			T31	324		T32	15907		T33	558903
all_values[10]	12797435	1			T31	324		T32	15907		T33	558903
all_values[11]	12797435	1			T31	324		T32	15907		T33	558903
all_values[12]	12797435	1			T31	324		T32	15907		T33	558903
all_values[13]	12797435	1			T31	324		T32	15907		T33	558903
all_values[14]	12797435	1			T31	324		T32	15907		T33	558903
all_values[15]	12797435	1			T31	324		T32	15907		T33	558903
all_values[16]	12797435	1			T31	324		T32	15907		T33	558903
all_values[17]	12797435	1			T31	324		T32	15907		T33	558903
all_values[18]	12797435	1			T31	324		T32	15907		T33	558903
all_values[19]	12797435	1			T31	324		T32	15907		T33	558903
all_values[20]	12797435	1			T31	324		T32	15907		T33	558903
all_values[21]	12797435	1			T31	324		T32	15907		T33	558903
all_values[22]	12797435	1			T31	324		T32	15907		T33	558903
all_values[23]	12797435	1			T31	324		T32	15907		T33	558903
all_values[24]	12797435	1			T31	324		T32	15907		T33	558903
all_values[25]	12797435	1			T31	324		T32	15907		T33	558903
all_values[26]	12797435	1			T31	324		T32	15907		T33	558903
all_values[27]	12797435	1			T31	324		T32	15907		T33	558903
all_values[28]	12797435	1			T31	324		T32	15907		T33	558903
all_values[29]	12797435	1			T31	324		T32	15907		T33	558903
all_values[30]	12797435	1			T31	324		T32	15907		T33	558903
all_values[31]	12797435	1			T31	324		T32	15907		T33	558903

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

239005151

1

T31

10368

T32

509024

T33

901566

auto[1]

170512769

1

T33

886923

T19

1175

T1

978

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

100984766

1

T31

10368

T32

509024

T33

176216

auto[1]

308533154

1

T33

161227

T19

1815

T1

1455

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

404986528

1

T31

10368

T32

509024

T33

176647

auto[1]

4531392

1

T33

220172

T19

262

T1

242

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2645431	1			T31	324		T32	15907		T33	29400
all_values[0]	auto[0]	auto[0]	auto[1]	4784949	1			T33	251163		T19	37		T1	21
all_values[0]	auto[0]	auto[1]	auto[0]	516811	1			T33	26249		T19	21		T1	14
all_values[0]	auto[0]	auto[1]	auto[1]	4708956	1			T33	245165		T19	15		T1	22
all_values[0]	auto[1]	auto[0]	auto[1]	71008	1			T33	3436		T19	7		T1	5
all_values[0]	auto[1]	auto[1]	auto[1]	70280	1			T33	3490		T19	2		T1	2
all_values[1]	auto[0]	auto[0]	auto[0]	2639007	1			T31	324		T32	15907		T33	26580
all_values[1]	auto[0]	auto[0]	auto[1]	4758160	1			T33	254820		T19	21		T1	20
all_values[1]	auto[0]	auto[1]	auto[0]	517595	1			T33	25156		T19	22		T1	22
all_values[1]	auto[0]	auto[1]	auto[1]	4740866	1			T33	245323		T19	11		T1	18
all_values[1]	auto[1]	auto[0]	auto[1]	71125	1			T33	3543		T19	4		T1	6
all_values[1]	auto[1]	auto[1]	auto[1]	70682	1			T33	3481		T19	2		T1	5
all_values[2]	auto[0]	auto[0]	auto[0]	2640733	1			T31	324		T32	15907		T33	30132
all_values[2]	auto[0]	auto[0]	auto[1]	4770408	1			T33	249132		T19	39		T1	20
all_values[2]	auto[0]	auto[1]	auto[0]	512794	1			T33	27013		T19	16		T1	22
all_values[2]	auto[0]	auto[1]	auto[1]	4731974	1			T33	245687		T19	23		T1	26
all_values[2]	auto[1]	auto[0]	auto[1]	70728	1			T33	3464		T19	5		T1	4
all_values[2]	auto[1]	auto[1]	auto[1]	70798	1			T33	3475		T19	1		T1	4
all_values[3]	auto[0]	auto[0]	auto[0]	2641532	1			T31	324		T32	15907		T33	27518
all_values[3]	auto[0]	auto[0]	auto[1]	4739286	1			T33	242557		T19	46		T1	29
all_values[3]	auto[0]	auto[1]	auto[0]	515431	1			T33	26606		T19	23		T1	1
all_values[3]	auto[0]	auto[1]	auto[1]	4759826	1			T33	255411		T19	10		T1	2
all_values[3]	auto[1]	auto[0]	auto[1]	70713	1			T33	3344		T19	7		T1	8
all_values[3]	auto[1]	auto[1]	auto[1]	70647	1			T33	3467		T19	1		T1	1
all_values[4]	auto[0]	auto[0]	auto[0]	2641315	1			T31	324		T32	15907		T33	26599
all_values[4]	auto[0]	auto[0]	auto[1]	4738694	1			T33	247663		T19	47		T1	8
all_values[4]	auto[0]	auto[1]	auto[0]	522153	1			T33	27383		T19	13		T1	24
all_values[4]	auto[0]	auto[1]	auto[1]	4753977	1			T33	250406		T1	20		T12	13893
all_values[4]	auto[1]	auto[0]	auto[1]	71033	1			T33	3352		T19	8		T1	2
all_values[4]	auto[1]	auto[1]	auto[1]	70263	1			T33	3500		T19	1		T1	3
all_values[5]	auto[0]	auto[0]	auto[0]	2643423	1			T31	324		T32	15907		T33	28677
all_values[5]	auto[0]	auto[0]	auto[1]	4753911	1			T33	241152		T19	49		T1	28
all_values[5]	auto[0]	auto[1]	auto[0]	513806	1			T33	26897		T19	18		T1	21
all_values[5]	auto[0]	auto[1]	auto[1]	4744941	1			T33	255342		T19	3		T1	9
all_values[5]	auto[1]	auto[0]	auto[1]	70971	1			T33	3356		T19	7		T1	5
all_values[5]	auto[1]	auto[1]	auto[1]	70383	1			T33	3479		T19	1		T12	163
all_values[6]	auto[0]	auto[0]	auto[0]	2637696	1			T31	324		T32	15907		T33	28517
all_values[6]	auto[0]	auto[0]	auto[1]	4741585	1			T33	240808		T19	32		T1	11
all_values[6]	auto[0]	auto[1]	auto[0]	507831	1			T33	26089		T19	18		T1	17
all_values[6]	auto[0]	auto[1]	auto[1]	4768438	1			T33	256613		T19	25		T1	17
all_values[6]	auto[1]	auto[0]	auto[1]	70683	1			T33	3410		T19	9		T1	7
all_values[6]	auto[1]	auto[1]	auto[1]	71202	1			T33	3466		T19	3		T1	2
all_values[7]	auto[0]	auto[0]	auto[0]	2637277	1			T31	324		T32	15907		T33	28713
all_values[7]	auto[0]	auto[0]	auto[1]	4725999	1			T33	247900		T19	50		T1	13
all_values[7]	auto[0]	auto[1]	auto[0]	517946	1			T33	28455		T19	14		T1	22
all_values[7]	auto[0]	auto[1]	auto[1]	4774381	1			T33	246949		T19	5		T1	18
all_values[7]	auto[1]	auto[0]	auto[1]	71190	1			T33	3497		T19	6		T1	6
all_values[7]	auto[1]	auto[1]	auto[1]	70642	1			T33	3389		T19	2		T1	5
all_values[8]	auto[0]	auto[0]	auto[0]	2646671	1			T31	324		T32	15907		T33	28248
all_values[8]	auto[0]	auto[0]	auto[1]	4764862	1			T33	254981		T19	30		T1	24
all_values[8]	auto[0]	auto[1]	auto[0]	512461	1			T33	24174		T19	27		T1	17
all_values[8]	auto[0]	auto[1]	auto[1]	4731627	1			T33	244543		T19	20		T1	15
all_values[8]	auto[1]	auto[0]	auto[1]	71550	1			T33	3526		T19	4		T1	2
all_values[8]	auto[1]	auto[1]	auto[1]	70264	1			T33	3431		T1	2		T12	201
all_values[9]	auto[0]	auto[0]	auto[0]	2646382	1			T31	324		T32	15907		T33	31088
all_values[9]	auto[0]	auto[0]	auto[1]	4768644	1			T33	248927		T19	55		T1	19
all_values[9]	auto[0]	auto[1]	auto[0]	518009	1			T33	26192		T19	10		T1	12
all_values[9]	auto[0]	auto[1]	auto[1]	4722886	1			T33	245821		T19	2		T1	24
all_values[9]	auto[1]	auto[0]	auto[1]	70951	1			T33	3410		T19	8		T1	5
all_values[9]	auto[1]	auto[1]	auto[1]	70563	1			T33	3465		T19	1		T1	3
all_values[10]	auto[0]	auto[0]	auto[0]	2640626	1			T31	324		T32	15907		T33	27236
all_values[10]	auto[0]	auto[0]	auto[1]	4758739	1			T33	254062		T19	27		T1	24
all_values[10]	auto[0]	auto[1]	auto[0]	523121	1			T33	26973		T19	32		T1	10
all_values[10]	auto[0]	auto[1]	auto[1]	4733277	1			T33	243670		T19	16		T1	4
all_values[10]	auto[1]	auto[0]	auto[1]	70564	1			T33	3377		T19	5		T1	4
all_values[10]	auto[1]	auto[1]	auto[1]	71108	1			T33	3585		T19	2		T12	198
all_values[11]	auto[0]	auto[0]	auto[0]	2644742	1			T31	324		T32	15907		T33	28082
all_values[11]	auto[0]	auto[0]	auto[1]	4759178	1			T33	243793		T19	30		T1	38
all_values[11]	auto[0]	auto[1]	auto[0]	508704	1			T33	25792		T19	34		T12	1411
all_values[11]	auto[0]	auto[1]	auto[1]	4743272	1			T33	254384		T19	10		T1	7
all_values[11]	auto[1]	auto[0]	auto[1]	71423	1			T33	3340		T19	5		T1	6
all_values[11]	auto[1]	auto[1]	auto[1]	70116	1			T33	3512		T19	4		T1	1
all_values[12]	auto[0]	auto[0]	auto[0]	2635616	1			T31	324		T32	15907		T33	27626
all_values[12]	auto[0]	auto[0]	auto[1]	4775350	1			T33	256990		T19	38		T1	25
all_values[12]	auto[0]	auto[1]	auto[0]	518109	1			T33	26715		T19	21		T1	16
all_values[12]	auto[0]	auto[1]	auto[1]	4726684	1			T33	240670		T19	18		T1	14
all_values[12]	auto[1]	auto[0]	auto[1]	71260	1			T33	3430		T19	5		T1	5
all_values[12]	auto[1]	auto[1]	auto[1]	70416	1			T33	3472		T19	1		T1	3
all_values[13]	auto[0]	auto[0]	auto[0]	2635881	1			T31	324		T32	15907		T33	28626
all_values[13]	auto[0]	auto[0]	auto[1]	4740736	1			T33	253145		T19	27		T1	33
all_values[13]	auto[0]	auto[1]	auto[0]	515329	1			T33	25610		T19	21		T1	5
all_values[13]	auto[0]	auto[1]	auto[1]	4763911	1			T33	244618		T19	26		T12	12773
all_values[13]	auto[1]	auto[0]	auto[1]	70751	1			T33	3605		T19	8		T1	6
all_values[13]	auto[1]	auto[1]	auto[1]	70827	1			T33	3299		T19	4		T1	1
all_values[14]	auto[0]	auto[0]	auto[0]	2635404	1			T31	324		T32	15907		T33	27440
all_values[14]	auto[0]	auto[0]	auto[1]	4754031	1			T33	251015		T19	32		T1	21
all_values[14]	auto[0]	auto[1]	auto[0]	513086	1			T33	27831		T19	30		T1	6
all_values[14]	auto[0]	auto[1]	auto[1]	4753229	1			T33	245692		T19	21		T1	24
all_values[14]	auto[1]	auto[0]	auto[1]	71516	1			T33	3441		T19	4		T1	4
all_values[14]	auto[1]	auto[1]	auto[1]	70169	1			T33	3484		T19	2		T1	3
all_values[15]	auto[0]	auto[0]	auto[0]	2643214	1			T31	324		T32	15907		T33	29614
all_values[15]	auto[0]	auto[0]	auto[1]	4770316	1			T33	247725		T19	44		T1	22
all_values[15]	auto[0]	auto[1]	auto[0]	511917	1			T33	26327		T19	21		T1	17
all_values[15]	auto[0]	auto[1]	auto[1]	4731066	1			T33	248354		T19	6		T1	18
all_values[15]	auto[1]	auto[0]	auto[1]	70846	1			T33	3446		T19	8		T1	5
all_values[15]	auto[1]	auto[1]	auto[1]	70076	1			T33	3437		T19	1		T1	4
all_values[16]	auto[0]	auto[0]	auto[0]	2640966	1			T31	324		T32	15907		T33	28277
all_values[16]	auto[0]	auto[0]	auto[1]	4764776	1			T33	251467		T19	29		T1	27
all_values[16]	auto[0]	auto[1]	auto[0]	511617	1			T33	29437		T19	31		T1	12
all_values[16]	auto[0]	auto[1]	auto[1]	4738562	1			T33	242840		T19	21		T1	23
all_values[16]	auto[1]	auto[0]	auto[1]	71194	1			T33	3454		T19	4		T1	6
all_values[16]	auto[1]	auto[1]	auto[1]	70320	1			T33	3428		T19	2		T1	3
all_values[17]	auto[0]	auto[0]	auto[0]	2634762	1			T31	324		T32	15907		T33	28355
all_values[17]	auto[0]	auto[0]	auto[1]	4735861	1			T33	256746		T19	53		T1	25
all_values[17]	auto[0]	auto[1]	auto[0]	514968	1			T33	24749		T19	7		T1	10
all_values[17]	auto[0]	auto[1]	auto[1]	4769819	1			T33	242177		T1	9		T12	13201
all_values[17]	auto[1]	auto[0]	auto[1]	71273	1			T33	3487		T19	8		T1	7
all_values[17]	auto[1]	auto[1]	auto[1]	70752	1			T33	3389		T1	2		T12	178
all_values[18]	auto[0]	auto[0]	auto[0]	2637324	1			T31	324		T32	15907		T33	26440
all_values[18]	auto[0]	auto[0]	auto[1]	4751319	1			T33	249000		T19	29		T1	16
all_values[18]	auto[0]	auto[1]	auto[0]	513283	1			T33	25925		T19	19		T1	22
all_values[18]	auto[0]	auto[1]	auto[1]	4753664	1			T33	250724		T19	4		T1	20
all_values[18]	auto[1]	auto[0]	auto[1]	71292	1			T33	3432		T19	5		T1	6
all_values[18]	auto[1]	auto[1]	auto[1]	70553	1			T33	3382		T19	3		T1	2
all_values[19]	auto[0]	auto[0]	auto[0]	2640774	1			T31	324		T32	15907		T33	31648
all_values[19]	auto[0]	auto[0]	auto[1]	4764550	1			T33	252749		T19	43		T1	24
all_values[19]	auto[0]	auto[1]	auto[0]	513907	1			T33	27422		T19	23		T1	9
all_values[19]	auto[0]	auto[1]	auto[1]	4736294	1			T33	240161		T19	7		T1	4
all_values[19]	auto[1]	auto[0]	auto[1]	71198	1			T33	3457		T19	8		T1	6
all_values[19]	auto[1]	auto[1]	auto[1]	70712	1			T33	3466		T19	2		T12	176
all_values[20]	auto[0]	auto[0]	auto[0]	2640133	1			T31	324		T32	15907		T33	28369
all_values[20]	auto[0]	auto[0]	auto[1]	4774891	1			T33	242059		T19	37		T1	19
all_values[20]	auto[0]	auto[1]	auto[0]	515236	1			T33	26504		T19	20		T1	22
all_values[20]	auto[0]	auto[1]	auto[1]	4725507	1			T33	255071		T19	14		T1	13
all_values[20]	auto[1]	auto[0]	auto[1]	71149	1			T33	3421		T19	5		T1	3
all_values[20]	auto[1]	auto[1]	auto[1]	70519	1			T33	3479		T19	2		T1	2
all_values[21]	auto[0]	auto[0]	auto[0]	2641111	1			T31	324		T32	15907		T33	29190
all_values[21]	auto[0]	auto[0]	auto[1]	4778947	1			T33	250604		T19	30		T1	17
all_values[21]	auto[0]	auto[1]	auto[0]	515392	1			T33	25034		T19	30		T1	11
all_values[21]	auto[0]	auto[1]	auto[1]	4720197	1			T33	247238		T19	17		T1	16
all_values[21]	auto[1]	auto[0]	auto[1]	71748	1			T33	3457		T19	4		T1	8
all_values[21]	auto[1]	auto[1]	auto[1]	70040	1			T33	3380		T19	3		T1	2
all_values[22]	auto[0]	auto[0]	auto[0]	2645626	1			T31	324		T32	15907		T33	28438
all_values[22]	auto[0]	auto[0]	auto[1]	4752528	1			T33	245535		T19	48		T1	32
all_values[22]	auto[0]	auto[1]	auto[0]	513078	1			T33	26632		T19	19		T1	15
all_values[22]	auto[0]	auto[1]	auto[1]	4744952	1			T33	251480		T19	8		T1	13
all_values[22]	auto[1]	auto[0]	auto[1]	71092	1			T33	3470		T19	9		T1	4
all_values[22]	auto[1]	auto[1]	auto[1]	70159	1			T33	3348		T1	2		T12	185
all_values[23]	auto[0]	auto[0]	auto[0]	2636034	1			T31	324		T32	15907		T33	31182
all_values[23]	auto[0]	auto[0]	auto[1]	4753478	1			T33	246645		T19	42		T1	34
all_values[23]	auto[0]	auto[1]	auto[0]	516591	1			T33	25690		T19	16		T1	7
all_values[23]	auto[0]	auto[1]	auto[1]	4749307	1			T33	248498		T19	25		T1	19
all_values[23]	auto[1]	auto[0]	auto[1]	71157	1			T33	3535		T19	7		T1	8
all_values[23]	auto[1]	auto[1]	auto[1]	70868	1			T33	3353		T19	2		T1	1
all_values[24]	auto[0]	auto[0]	auto[0]	2638254	1			T31	324		T32	15907		T33	30406
all_values[24]	auto[0]	auto[0]	auto[1]	4764676	1			T33	253091		T19	24		T1	23
all_values[24]	auto[0]	auto[1]	auto[0]	515845	1			T33	27262		T19	19		T1	7
all_values[24]	auto[0]	auto[1]	auto[1]	4736806	1			T33	241247		T19	7		T1	25
all_values[24]	auto[1]	auto[0]	auto[1]	71112	1			T33	3573		T19	6		T1	7
all_values[24]	auto[1]	auto[1]	auto[1]	70742	1			T33	3324		T19	1		T1	1
all_values[25]	auto[0]	auto[0]	auto[0]	2637315	1			T31	324		T32	15907		T33	29558
all_values[25]	auto[0]	auto[0]	auto[1]	4761982	1			T33	254869		T19	33		T1	20
all_values[25]	auto[0]	auto[1]	auto[0]	521250	1			T33	27091		T19	13		T1	12
all_values[25]	auto[0]	auto[1]	auto[1]	4735788	1			T33	240628		T19	8		T1	10
all_values[25]	auto[1]	auto[0]	auto[1]	70597	1			T33	3351		T19	8		T1	5
all_values[25]	auto[1]	auto[1]	auto[1]	70503	1			T33	3406		T19	3		T1	4
all_values[26]	auto[0]	auto[0]	auto[0]	2636252	1			T31	324		T32	15907		T33	28110
all_values[26]	auto[0]	auto[0]	auto[1]	4772983	1			T33	246846		T19	23		T1	24
all_values[26]	auto[0]	auto[1]	auto[0]	514003	1			T33	27715		T19	29		T1	22
all_values[26]	auto[0]	auto[1]	auto[1]	4732678	1			T33	249341		T19	29		T1	9
all_values[26]	auto[1]	auto[0]	auto[1]	70697	1			T33	3506		T19	3		T1	4
all_values[26]	auto[1]	auto[1]	auto[1]	70822	1			T33	3385		T19	2		T1	2
all_values[27]	auto[0]	auto[0]	auto[0]	2640203	1			T31	324		T32	15907		T33	28555
all_values[27]	auto[0]	auto[0]	auto[1]	4739810	1			T33	252754		T19	35		T1	13
all_values[27]	auto[0]	auto[1]	auto[0]	516379	1			T33	25984		T19	14		T1	12
all_values[27]	auto[0]	auto[1]	auto[1]	4759176	1			T33	244745		T19	3		T1	34
all_values[27]	auto[1]	auto[0]	auto[1]	70739	1			T33	3467		T19	7		T1	3
all_values[27]	auto[1]	auto[1]	auto[1]	71128	1			T33	3398		T19	2		T1	7
all_values[28]	auto[0]	auto[0]	auto[0]	2640151	1			T31	324		T32	15907		T33	27686
all_values[28]	auto[0]	auto[0]	auto[1]	4747723	1			T33	252620		T19	30		T1	18
all_values[28]	auto[0]	auto[1]	auto[0]	520648	1			T33	28295		T19	36		T1	9
all_values[28]	auto[0]	auto[1]	auto[1]	4747399	1			T33	243545		T19	10		T1	16
all_values[28]	auto[1]	auto[0]	auto[1]	70573	1			T33	3404		T19	6		T1	5
all_values[28]	auto[1]	auto[1]	auto[1]	70941	1			T33	3353		T19	3		T1	3
all_values[29]	auto[0]	auto[0]	auto[0]	2645252	1			T31	324		T32	15907		T33	30597
all_values[29]	auto[0]	auto[0]	auto[1]	4736532	1			T33	246997		T19	31		T1	36
all_values[29]	auto[0]	auto[1]	auto[0]	516610	1			T33	25202		T19	20		T1	9
all_values[29]	auto[0]	auto[1]	auto[1]	4757310	1			T33	249179		T19	20		T1	2
all_values[29]	auto[1]	auto[0]	auto[1]	71556	1			T33	3510		T19	8		T1	10
all_values[29]	auto[1]	auto[1]	auto[1]	70175	1			T33	3418		T19	2		T12	196
all_values[30]	auto[0]	auto[0]	auto[0]	2636207	1			T31	324		T32	15907		T33	27489
all_values[30]	auto[0]	auto[0]	auto[1]	4751360	1			T33	253978		T19	11		T1	26
all_values[30]	auto[0]	auto[1]	auto[0]	514567	1			T33	25194		T19	51		T1	6
all_values[30]	auto[0]	auto[1]	auto[1]	4753624	1			T33	245392		T19	7		T1	19
all_values[30]	auto[1]	auto[0]	auto[1]	71254	1			T33	3346		T19	6		T1	3
all_values[30]	auto[1]	auto[1]	auto[1]	70423	1			T33	3504		T19	3		T1	2
all_values[31]	auto[0]	auto[0]	auto[0]	2644102	1			T31	324		T32	15907		T33	27106
all_values[31]	auto[0]	auto[0]	auto[1]	4785544	1			T33	248094		T19	41		T1	28
all_values[31]	auto[0]	auto[1]	auto[0]	516873	1			T33	25067		T19	16		T1	19
all_values[31]	auto[0]	auto[1]	auto[1]	4709560	1			T33	251756		T19	19		T1	5
all_values[31]	auto[1]	auto[0]	auto[1]	70984	1			T33	3430		T19	7		T1	4
all_values[31]	auto[1]	auto[1]	auto[1]	70372	1			T33	3450		T19	3		T1	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal