Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[1]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[2]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[3]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[4]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[5]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[6]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[7]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[8]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[9]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[10]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[11]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[12]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[13]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[14]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[15]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[16]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[17]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[18]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[19]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[20]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[21]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[22]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[23]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[24]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[25]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[26]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[27]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[28]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[29]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[30]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[31]	12636370	1			T31	630		T32	15907		T33	553615

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

242216551

1

T31

16120

T32

256349

T33

117293

auto[1]

162147289

1

T31

4040

T32

252675

T33

598635

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

324168509

1

T31

15193

T32

509024

T33

136976

auto[1]

80195331

1

T31

4967

T33

401806

T19

222

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300777069

1

T31

10726

T32

509024

T33

124685

auto[1]

103586771

1

T31

9434

T33

524709

T19

841

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4699962	1			T31	204		T32	8093		T33	208485
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3433888	1			T31	28		T32	7814		T33	117937
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1264240	1			T31	127		T33	64098		T19	7
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1603180	1			T31	146		T33	94136		T19	17
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	384010	1			T31	30		T33	6823		T19	7
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1251090	1			T31	95		T33	62136		T12	3173
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4694454	1			T31	256		T32	7716		T33	208306
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3441692	1			T31	24		T32	8191		T33	118023
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1259033	1			T31	77		T33	63067		T19	3
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1604523	1			T31	186		T33	94162		T19	11
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	384509	1			T31	27		T33	6920		T19	5
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1252159	1			T31	60		T33	63137		T19	2
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4698618	1			T31	176		T32	8893		T33	208675
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3436382	1			T31	30		T32	7014		T33	117710
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1261829	1			T31	91		T33	63979		T19	8
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1600385	1			T31	205		T33	93473		T19	31
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	380496	1			T31	30		T33	6908		T19	10
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1258660	1			T31	98		T33	62870		T19	2
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4697711	1			T31	109		T32	8040		T33	208230
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3443277	1			T31	18		T32	7867		T33	118126
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1257073	1			T31	76		T33	63713		T1	4
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1606653	1			T31	257		T33	94063		T19	13
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	382661	1			T31	40		T33	6761		T19	26
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1248995	1			T31	130		T33	62722		T19	7
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4690998	1			T31	264		T32	8120		T33	208791
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3446963	1			T31	17		T32	7787		T33	117283
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1260514	1			T31	92		T33	62933		T11	4
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1605509	1			T31	184		T33	94225		T19	12
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	383026	1			T31	31		T33	6884		T19	8
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1249360	1			T31	42		T33	63499		T19	14
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4698304	1			T31	232		T32	8128		T33	207185
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3438407	1			T31	32		T32	7779		T33	117981
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1258663	1			T31	83		T33	63584		T19	3
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1605036	1			T31	183		T33	94439		T19	9
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	382855	1			T31	20		T33	6809		T19	1
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1253105	1			T31	80		T33	63617		T1	4
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4703135	1			T31	151		T32	9315		T33	208657
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3437963	1			T31	27		T32	6592		T33	117613
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1264185	1			T31	63		T33	64916		T19	5
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1602942	1			T31	270		T33	94234		T19	23
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	382229	1			T31	31		T33	6742		T19	12
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1245916	1			T31	88		T33	61453		T1	15
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4697904	1			T31	262		T32	7288		T33	209114
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3435717	1			T31	33		T32	8619		T33	117726
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1260331	1			T31	125		T33	63640		T19	4
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1606591	1			T31	140		T33	93748		T19	16
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	383020	1			T31	17		T33	6743		T19	8
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1252807	1			T31	53		T33	62644		T1	11
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4691828	1			T31	119		T32	7670		T33	208734
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3445750	1			T31	26		T32	8237		T33	117623
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1260464	1			T31	80		T33	63525		T1	2
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1607055	1			T31	280		T33	94512		T19	9
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	380310	1			T31	28		T33	6810		T19	14
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1250963	1			T31	97		T33	62411		T19	2
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4715236	1			T31	196		T32	8461		T33	207941
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3426959	1			T31	32		T32	7446		T33	117616
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1263018	1			T31	123		T33	64203		T19	5
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1600752	1			T31	226		T33	94465		T19	6
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	381323	1			T31	22		T33	6934		T19	6
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1249082	1			T31	31		T33	62456		T19	8
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4708998	1			T31	198		T32	8116		T33	208569
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3432462	1			T31	25		T32	7791		T33	118229
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1259821	1			T31	63		T33	64470		T1	12
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1602927	1			T31	196		T33	93484		T19	9
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	379850	1			T31	43		T33	6829		T19	23
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1252312	1			T31	105		T33	62034		T19	11
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4697838	1			T31	198		T32	7845		T33	206858
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3433399	1			T31	28		T32	8062		T33	117886
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1261464	1			T31	54		T33	63038		T19	6
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1607285	1			T31	231		T33	95873		T19	18
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	381483	1			T31	36		T33	6892		T19	8
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1254901	1			T31	83		T33	63068		T19	2
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4700559	1			T31	264		T32	8824		T33	210248
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3439098	1			T31	29		T32	7083		T33	117682
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1261863	1			T31	71		T33	63247		T19	8
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1607437	1			T31	171		T33	94115		T19	9
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	381086	1			T31	31		T33	6722		T19	11
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1246327	1			T31	64		T33	61601		T19	1
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4702707	1			T31	217		T32	7673		T33	209425
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3438596	1			T31	22		T32	8234		T33	117835
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1261841	1			T31	99		T33	62100		T19	5
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1601899	1			T31	202		T33	94955		T19	10
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	381916	1			T31	36		T33	6867		T19	9
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1249411	1			T31	54		T33	62433		T19	1
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4703155	1			T31	295		T32	8093		T33	208612
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3436527	1			T31	23		T32	7814		T33	117664
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1258136	1			T31	71		T33	63322		T19	7
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1611088	1			T31	176		T33	95691		T19	18
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	381071	1			T31	19		T33	6810		T19	17
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1246393	1			T31	46		T33	61516		T19	9
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4693847	1			T31	289		T32	7889		T33	210043
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3450527	1			T31	34		T32	8018		T33	117960
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1260622	1			T31	59		T33	63404		T19	2
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1602904	1			T31	167		T33	93450		T19	16
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	381125	1			T31	23		T33	6668		T19	14
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1247345	1			T31	58		T33	62090		T11	3
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4706542	1			T31	182		T32	8185		T33	210641
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3436972	1			T31	29		T32	7722		T33	117293
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1253341	1			T31	90		T33	61883		T19	8
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1609565	1			T31	221		T33	94689		T19	17
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	382937	1			T31	27		T33	6869		T19	1
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1247013	1			T31	81		T33	62240		T1	3
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4712740	1			T31	202		T32	8056		T33	208580
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3431946	1			T31	36		T32	7851		T33	117936
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1250827	1			T31	64		T33	61647		T19	1
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1612220	1			T31	230		T33	96711		T19	18
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	383262	1			T31	30		T33	6822		T19	10
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1245375	1			T31	68		T33	61919		T19	2
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4710406	1			T31	229		T32	7798		T33	208634
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3433585	1			T31	32		T32	8109		T33	117903
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1252069	1			T31	81		T33	62409		T1	2
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1608792	1			T31	192		T33	95143		T19	4
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	382633	1			T31	27		T33	6899		T19	20
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1248885	1			T31	69		T33	62627		T19	7
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4703306	1			T31	292		T32	8744		T33	210152
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3435691	1			T31	39		T32	7163		T33	118028
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1258156	1			T31	106		T33	62335		T19	1
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1607442	1			T31	142		T33	94280		T19	24
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	382650	1			T31	21		T33	6619		T19	3
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1249125	1			T31	30		T33	62201		T11	2
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4712165	1			T31	236		T32	7690		T33	209509
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3431428	1			T31	21		T32	8217		T33	117649
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1255003	1			T31	88		T33	62847		T19	2
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1612490	1			T31	174		T33	94905		T19	19
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	383205	1			T31	46		T33	6732		T19	2
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1242079	1			T31	65		T33	61973		T19	12
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4699224	1			T31	238		T32	8909		T33	208570
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3442365	1			T31	32		T32	6998		T33	117821
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1255199	1			T31	61		T33	61987		T19	2
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1608427	1			T31	200		T33	95618		T19	2
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	383973	1			T31	20		T33	6982		T19	6
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1247182	1			T31	79		T33	62637		T19	2
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4710659	1			T31	202		T32	6805		T33	209122
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3437870	1			T31	15		T32	9102		T33	118014
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1256921	1			T31	42		T33	62289		T19	4
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1609131	1			T31	236		T33	95219		T19	5
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	380107	1			T31	31		T33	6502		T19	8
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1241682	1			T31	104		T33	62469		T19	4
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4711589	1			T31	265		T32	8206		T33	208497
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3434895	1			T31	27		T32	7701		T33	117882
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1254460	1			T31	82		T33	61892		T19	8
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1605689	1			T31	169		T33	95822		T19	8
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	382411	1			T31	25		T33	6797		T19	6
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1247326	1			T31	62		T33	62725		T1	21
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4713310	1			T31	242		T32	8549		T33	208049
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3429728	1			T31	34		T32	7358		T33	117754
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1259530	1			T31	72		T33	62639		T1	3
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1609302	1			T31	212		T33	96044		T19	21
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	383220	1			T31	16		T33	6948		T19	5
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1241280	1			T31	54		T33	62181		T19	2
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4707279	1			T31	188		T32	8719		T33	207644
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3440346	1			T31	22		T32	7188		T33	117705
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1256061	1			T31	77		T33	62978		T19	7
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1608314	1			T31	219		T33	96182		T19	3
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	383515	1			T31	30		T33	7166		T19	13
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1240855	1			T31	94		T33	61940		T19	4
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4710323	1			T31	230		T32	7013		T33	210824
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3434526	1			T31	37		T32	8894		T33	118000
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1257766	1			T31	115		T33	62563		T19	1
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1608255	1			T31	164		T33	94382		T19	33
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	381198	1			T31	11		T33	6666		T19	8
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1244302	1			T31	73		T33	61180		T19	3
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4693630	1			T31	258		T32	7602		T33	207684
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3440388	1			T31	30		T32	8305		T33	118049
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1260095	1			T31	116		T33	64046		T19	1
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1613395	1			T31	163		T33	94810		T19	19
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	383537	1			T31	19		T33	6867		T19	12
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1245325	1			T31	44		T33	62159		T19	2
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4702385	1			T31	235		T32	7309		T33	207515
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3439652	1			T31	54		T32	8598		T33	118169
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1253223	1			T31	99		T33	61797		T19	2
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1611177	1			T31	150		T33	95312		T19	9
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	380535	1			T31	14		T33	6934		T19	8
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1249398	1			T31	78		T33	63888		T19	5
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4702091	1			T31	236		T32	7720		T33	207166
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3440590	1			T31	28		T32	8187		T33	117733
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1254936	1			T31	87		T33	64609		T1	7
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1614583	1			T31	218		T33	95219		T19	6
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	383223	1			T31	21		T33	6672		T19	6
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1240947	1			T31	40		T33	62216		T19	2
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4715833	1			T31	205		T32	7887		T33	208746
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3429069	1			T31	24		T32	8020		T33	118272
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1255646	1			T31	82		T33	63484		T19	8
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1608902	1			T31	240		T33	93407		T19	14
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	382054	1			T31	25		T33	6752		T19	7
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1244866	1			T31	54		T33	62954		T19	5
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4711724	1			T31	237		T32	6993		T33	208355
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3434165	1			T31	31		T32	8914		T33	117455
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1261456	1			T31	84		T33	63825		T19	5
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1606455	1			T31	163		T33	94531		T19	8
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	379491	1			T31	27		T33	6851		T19	1
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1243079	1			T31	88		T33	62598		T1	14

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal