Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[1]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[2]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[3]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[4]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[5]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[6]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[7]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[8]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[9]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[10]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[11]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[12]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[13]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[14]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[15]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[16]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[17]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[18]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[19]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[20]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[21]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[22]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[23]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[24]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[25]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[26]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[27]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[28]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[29]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[30]	12636370	1			T31	630		T32	15907		T33	553615
bins_for_gpio_bits[31]	12636370	1			T31	630		T32	15907		T33	553615

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

242216551

1

T31

16120

T32

256349

T33

117293

auto[1]

162147289

1

T31

4040

T32

252675

T33

598635

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

242207157

1

T31

16114

T32

256349

T33

117293

auto[1]

162156683

1

T31

4046

T32

252675

T33

598637

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	7343703	1			T31	461		T32	8093		T33	355620
bins_for_gpio_bits[0]	auto[0]	auto[1]	223425	1			T31	15		T33	11099		T12	529
bins_for_gpio_bits[0]	auto[1]	auto[0]	223679	1			T31	16		T33	11099		T12	528
bins_for_gpio_bits[0]	auto[1]	auto[1]	4845563	1			T31	138		T32	7814		T33	175797
bins_for_gpio_bits[1]	auto[0]	auto[0]	7333814	1			T31	510		T32	7716		T33	354220
bins_for_gpio_bits[1]	auto[0]	auto[1]	223852	1			T31	9		T33	11312		T12	538
bins_for_gpio_bits[1]	auto[1]	auto[0]	224196	1			T31	9		T33	11315		T12	537
bins_for_gpio_bits[1]	auto[1]	auto[1]	4854508	1			T31	102		T32	8191		T33	176768
bins_for_gpio_bits[2]	auto[0]	auto[0]	7336565	1			T31	454		T32	8893		T33	354862
bins_for_gpio_bits[2]	auto[0]	auto[1]	223991	1			T31	17		T33	11264		T11	1
bins_for_gpio_bits[2]	auto[1]	auto[0]	224267	1			T31	18		T33	11265		T1	1
bins_for_gpio_bits[2]	auto[1]	auto[1]	4851547	1			T31	141		T32	7014		T33	176224
bins_for_gpio_bits[3]	auto[0]	auto[0]	7337736	1			T31	423		T32	8040		T33	354824
bins_for_gpio_bits[3]	auto[0]	auto[1]	223381	1			T31	18		T33	11182		T1	1
bins_for_gpio_bits[3]	auto[1]	auto[0]	223701	1			T31	19		T33	11182		T11	3
bins_for_gpio_bits[3]	auto[1]	auto[1]	4851552	1			T31	170		T32	7867		T33	176427
bins_for_gpio_bits[4]	auto[0]	auto[0]	7333546	1			T31	532		T32	8120		T33	354605
bins_for_gpio_bits[4]	auto[0]	auto[1]	223215	1			T31	8		T33	11344		T12	595
bins_for_gpio_bits[4]	auto[1]	auto[0]	223475	1			T31	8		T33	11344		T12	593
bins_for_gpio_bits[4]	auto[1]	auto[1]	4856134	1			T31	82		T32	7787		T33	176322
bins_for_gpio_bits[5]	auto[0]	auto[0]	7337708	1			T31	484		T32	8128		T33	353989
bins_for_gpio_bits[5]	auto[0]	auto[1]	223957	1			T31	14		T33	11219		T12	538
bins_for_gpio_bits[5]	auto[1]	auto[0]	224295	1			T31	14		T33	11219		T12	535
bins_for_gpio_bits[5]	auto[1]	auto[1]	4850410	1			T31	118		T32	7779		T33	177188
bins_for_gpio_bits[6]	auto[0]	auto[0]	7346867	1			T31	468		T32	9315		T33	356654
bins_for_gpio_bits[6]	auto[0]	auto[1]	223109	1			T31	16		T33	11153		T11	3
bins_for_gpio_bits[6]	auto[1]	auto[0]	223395	1			T31	16		T33	11153		T11	3
bins_for_gpio_bits[6]	auto[1]	auto[1]	4842999	1			T31	130		T32	6592		T33	174655
bins_for_gpio_bits[7]	auto[0]	auto[0]	7340857	1			T31	518		T32	7288		T33	355409
bins_for_gpio_bits[7]	auto[0]	auto[1]	223716	1			T31	9		T33	11093		T11	1
bins_for_gpio_bits[7]	auto[1]	auto[0]	223969	1			T31	9		T33	11093		T11	2
bins_for_gpio_bits[7]	auto[1]	auto[1]	4847828	1			T31	94		T32	8619		T33	176020
bins_for_gpio_bits[8]	auto[0]	auto[0]	7335452	1			T31	462		T32	7670		T33	355585
bins_for_gpio_bits[8]	auto[0]	auto[1]	223630	1			T31	16		T33	11185		T12	565
bins_for_gpio_bits[8]	auto[1]	auto[0]	223895	1			T31	17		T33	11186		T12	564
bins_for_gpio_bits[8]	auto[1]	auto[1]	4853393	1			T31	135		T32	8237		T33	175659
bins_for_gpio_bits[9]	auto[0]	auto[0]	7355257	1			T31	540		T32	8461		T33	355376
bins_for_gpio_bits[9]	auto[0]	auto[1]	223457	1			T31	5		T33	11231		T11	1
bins_for_gpio_bits[9]	auto[1]	auto[0]	223749	1			T31	5		T33	11233		T11	1
bins_for_gpio_bits[9]	auto[1]	auto[1]	4833907	1			T31	80		T32	7446		T33	175775
bins_for_gpio_bits[10]	auto[0]	auto[0]	7348318	1			T31	442		T32	8116		T33	355430
bins_for_gpio_bits[10]	auto[0]	auto[1]	223138	1			T31	15		T33	11092		T1	1
bins_for_gpio_bits[10]	auto[1]	auto[0]	223428	1			T31	15		T33	11093		T1	1
bins_for_gpio_bits[10]	auto[1]	auto[1]	4841486	1			T31	158		T32	7791		T33	176000
bins_for_gpio_bits[11]	auto[0]	auto[0]	7342450	1			T31	467		T32	7845		T33	354455
bins_for_gpio_bits[11]	auto[0]	auto[1]	223835	1			T31	16		T33	11314		T11	2
bins_for_gpio_bits[11]	auto[1]	auto[0]	224137	1			T31	16		T33	11314		T11	2
bins_for_gpio_bits[11]	auto[1]	auto[1]	4845948	1			T31	131		T32	8062		T33	176532
bins_for_gpio_bits[12]	auto[0]	auto[0]	7346254	1			T31	496		T32	8824		T33	356566
bins_for_gpio_bits[12]	auto[0]	auto[1]	223327	1			T31	10		T33	11042		T1	1
bins_for_gpio_bits[12]	auto[1]	auto[0]	223605	1			T31	10		T33	11044		T11	3
bins_for_gpio_bits[12]	auto[1]	auto[1]	4843184	1			T31	114		T32	7083		T33	174963
bins_for_gpio_bits[13]	auto[0]	auto[0]	7342969	1			T31	508		T32	7673		T33	355240
bins_for_gpio_bits[13]	auto[0]	auto[1]	223238	1			T31	10		T33	11239		T1	1
bins_for_gpio_bits[13]	auto[1]	auto[0]	223478	1			T31	10		T33	11240		T11	1
bins_for_gpio_bits[13]	auto[1]	auto[1]	4846685	1			T31	102		T32	8234		T33	175896
bins_for_gpio_bits[14]	auto[0]	auto[0]	7349137	1			T31	534		T32	8093		T33	356453
bins_for_gpio_bits[14]	auto[0]	auto[1]	222942	1			T31	8		T33	11172		T1	1
bins_for_gpio_bits[14]	auto[1]	auto[0]	223242	1			T31	8		T33	11172		T11	1
bins_for_gpio_bits[14]	auto[1]	auto[1]	4841049	1			T31	80		T32	7814		T33	174818
bins_for_gpio_bits[15]	auto[0]	auto[0]	7334139	1			T31	504		T32	7889		T33	355801
bins_for_gpio_bits[15]	auto[0]	auto[1]	222912	1			T31	11		T33	11095		T11	1
bins_for_gpio_bits[15]	auto[1]	auto[0]	223234	1			T31	11		T33	11096		T11	1
bins_for_gpio_bits[15]	auto[1]	auto[1]	4856085	1			T31	104		T32	8018		T33	175623
bins_for_gpio_bits[16]	auto[0]	auto[0]	7345539	1			T31	480		T32	8185		T33	356126
bins_for_gpio_bits[16]	auto[0]	auto[1]	223610	1			T31	13		T33	11087		T12	507
bins_for_gpio_bits[16]	auto[1]	auto[0]	223909	1			T31	13		T33	11087		T12	507
bins_for_gpio_bits[16]	auto[1]	auto[1]	4843312	1			T31	124		T32	7722		T33	175315
bins_for_gpio_bits[17]	auto[0]	auto[0]	7352147	1			T31	483		T32	8056		T33	355795
bins_for_gpio_bits[17]	auto[0]	auto[1]	223383	1			T31	13		T33	11143		T1	1
bins_for_gpio_bits[17]	auto[1]	auto[0]	223640	1			T31	13		T33	11143		T11	1
bins_for_gpio_bits[17]	auto[1]	auto[1]	4837200	1			T31	121		T32	7851		T33	175534
bins_for_gpio_bits[18]	auto[0]	auto[0]	7347128	1			T31	487		T32	7798		T33	354937
bins_for_gpio_bits[18]	auto[0]	auto[1]	223819	1			T31	15		T33	11248		T11	2
bins_for_gpio_bits[18]	auto[1]	auto[0]	224139	1			T31	15		T33	11249		T11	2
bins_for_gpio_bits[18]	auto[1]	auto[1]	4841284	1			T31	113		T32	8109		T33	176181
bins_for_gpio_bits[19]	auto[0]	auto[0]	7344898	1			T31	532		T32	8744		T33	355713
bins_for_gpio_bits[19]	auto[0]	auto[1]	223699	1			T31	8		T33	11053		T11	1
bins_for_gpio_bits[19]	auto[1]	auto[0]	224006	1			T31	8		T33	11054		T11	1
bins_for_gpio_bits[19]	auto[1]	auto[1]	4843767	1			T31	82		T32	7163		T33	175795
bins_for_gpio_bits[20]	auto[0]	auto[0]	7356108	1			T31	482		T32	7690		T33	356220
bins_for_gpio_bits[20]	auto[0]	auto[1]	223269	1			T31	16		T33	11041		T19	1
bins_for_gpio_bits[20]	auto[1]	auto[0]	223550	1			T31	16		T33	11041		T11	1
bins_for_gpio_bits[20]	auto[1]	auto[1]	4833443	1			T31	116		T32	8217		T33	175313
bins_for_gpio_bits[21]	auto[0]	auto[0]	7338901	1			T31	489		T32	8909		T33	354910
bins_for_gpio_bits[21]	auto[0]	auto[1]	223688	1			T31	10		T33	11264		T1	1
bins_for_gpio_bits[21]	auto[1]	auto[0]	223949	1			T31	10		T33	11265		T1	1
bins_for_gpio_bits[21]	auto[1]	auto[1]	4849832	1			T31	121		T32	6998		T33	176176
bins_for_gpio_bits[22]	auto[0]	auto[0]	7353223	1			T31	466		T32	6805		T33	355430
bins_for_gpio_bits[22]	auto[0]	auto[1]	223156	1			T31	14		T33	11199		T19	1
bins_for_gpio_bits[22]	auto[1]	auto[0]	223488	1			T31	14		T33	11200		T19	1
bins_for_gpio_bits[22]	auto[1]	auto[1]	4836503	1			T31	136		T32	9102		T33	175786
bins_for_gpio_bits[23]	auto[0]	auto[0]	7347791	1			T31	503		T32	8206		T33	354968
bins_for_gpio_bits[23]	auto[0]	auto[1]	223650	1			T31	13		T33	11242		T1	1
bins_for_gpio_bits[23]	auto[1]	auto[0]	223947	1			T31	13		T33	11243		T12	524
bins_for_gpio_bits[23]	auto[1]	auto[1]	4840982	1			T31	101		T32	7701		T33	176162
bins_for_gpio_bits[24]	auto[0]	auto[0]	7358947	1			T31	512		T32	8549		T33	355530
bins_for_gpio_bits[24]	auto[0]	auto[1]	222885	1			T31	13		T33	11202		T11	1
bins_for_gpio_bits[24]	auto[1]	auto[0]	223195	1			T31	14		T33	11202		T11	1
bins_for_gpio_bits[24]	auto[1]	auto[1]	4831343	1			T31	91		T32	7358		T33	175681
bins_for_gpio_bits[25]	auto[0]	auto[0]	7348441	1			T31	468		T32	8719		T33	355560
bins_for_gpio_bits[25]	auto[0]	auto[1]	222896	1			T31	16		T33	11243		T19	1
bins_for_gpio_bits[25]	auto[1]	auto[0]	223213	1			T31	16		T33	11244		T1	1
bins_for_gpio_bits[25]	auto[1]	auto[1]	4841820	1			T31	130		T32	7188		T33	175568
bins_for_gpio_bits[26]	auto[0]	auto[0]	7352750	1			T31	495		T32	7013		T33	356664
bins_for_gpio_bits[26]	auto[0]	auto[1]	223289	1			T31	14		T33	11104		T1	3
bins_for_gpio_bits[26]	auto[1]	auto[0]	223594	1			T31	14		T33	11105		T1	1
bins_for_gpio_bits[26]	auto[1]	auto[1]	4836737	1			T31	107		T32	8894		T33	174742
bins_for_gpio_bits[27]	auto[0]	auto[0]	7342923	1			T31	527		T32	7602		T33	355396
bins_for_gpio_bits[27]	auto[0]	auto[1]	223895	1			T31	10		T33	11141		T12	572
bins_for_gpio_bits[27]	auto[1]	auto[0]	224197	1			T31	10		T33	11144		T12	571
bins_for_gpio_bits[27]	auto[1]	auto[1]	4845355	1			T31	83		T32	8305		T33	175934
bins_for_gpio_bits[28]	auto[0]	auto[0]	7342341	1			T31	467		T32	7309		T33	353353
bins_for_gpio_bits[28]	auto[0]	auto[1]	224118	1			T31	16		T33	11271		T12	535
bins_for_gpio_bits[28]	auto[1]	auto[0]	224444	1			T31	17		T33	11271		T12	533
bins_for_gpio_bits[28]	auto[1]	auto[1]	4845467	1			T31	130		T32	8598		T33	177720
bins_for_gpio_bits[29]	auto[0]	auto[0]	7348405	1			T31	532		T32	7720		T33	355888
bins_for_gpio_bits[29]	auto[0]	auto[1]	222914	1			T31	9		T33	11106		T12	530
bins_for_gpio_bits[29]	auto[1]	auto[0]	223205	1			T31	9		T33	11106		T12	528
bins_for_gpio_bits[29]	auto[1]	auto[1]	4841846	1			T31	80		T32	8187		T33	175515
bins_for_gpio_bits[30]	auto[0]	auto[0]	7356395	1			T31	515		T32	7887		T33	354354
bins_for_gpio_bits[30]	auto[0]	auto[1]	223691	1			T31	12		T33	11283		T11	2
bins_for_gpio_bits[30]	auto[1]	auto[0]	223986	1			T31	12		T33	11283		T11	2
bins_for_gpio_bits[30]	auto[1]	auto[1]	4832298	1			T31	91		T32	8020		T33	176695
bins_for_gpio_bits[31]	auto[0]	auto[0]	7355935	1			T31	469		T32	6993		T33	355487
bins_for_gpio_bits[31]	auto[0]	auto[1]	223426	1			T31	15		T33	11223		T1	1
bins_for_gpio_bits[31]	auto[1]	auto[0]	223700	1			T31	15		T33	11224		T1	1
bins_for_gpio_bits[31]	auto[1]	auto[1]	4833309	1			T31	131		T32	8914		T33	175681