Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7501388 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
283999 |
| auto[1] |
5296047 |
1 |
|
|
T33 |
274904 |
|
T19 |
38 |
|
T1 |
38 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12125118 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
523178 |
| auto[1] |
672317 |
1 |
|
|
T33 |
35725 |
|
T19 |
1 |
|
T1 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7480625 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
278524 |
| auto[1] |
5316810 |
1 |
|
|
T33 |
280379 |
|
T19 |
35 |
|
T1 |
43 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2346296 |
1 |
|
|
T33 |
122394 |
|
T19 |
29 |
|
T1 |
27 |
| auto[1] |
auto[0] |
auto[1] |
339409 |
1 |
|
|
T33 |
17713 |
|
T19 |
1 |
|
T12 |
884 |
| auto[1] |
auto[1] |
auto[0] |
2298197 |
1 |
|
|
T33 |
122260 |
|
T19 |
5 |
|
T1 |
15 |
| auto[1] |
auto[1] |
auto[1] |
332908 |
1 |
|
|
T33 |
18012 |
|
T1 |
1 |
|
T12 |
875 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7468292 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
284943 |
| auto[1] |
5329143 |
1 |
|
|
T33 |
273960 |
|
T19 |
35 |
|
T1 |
45 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12121323 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
521812 |
| auto[1] |
676112 |
1 |
|
|
T33 |
37091 |
|
T19 |
2 |
|
T12 |
2111 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7452780 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
271228 |
| auto[1] |
5344655 |
1 |
|
|
T33 |
287675 |
|
T19 |
58 |
|
T1 |
23 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2330987 |
1 |
|
|
T33 |
129776 |
|
T19 |
49 |
|
T1 |
13 |
| auto[1] |
auto[0] |
auto[1] |
337311 |
1 |
|
|
T33 |
19361 |
|
T19 |
2 |
|
T12 |
1041 |
| auto[1] |
auto[1] |
auto[0] |
2337556 |
1 |
|
|
T33 |
120808 |
|
T19 |
7 |
|
T1 |
10 |
| auto[1] |
auto[1] |
auto[1] |
338801 |
1 |
|
|
T33 |
17730 |
|
T12 |
1070 |
|
T14 |
16 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7469929 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
284675 |
| auto[1] |
5327506 |
1 |
|
|
T33 |
274228 |
|
T19 |
50 |
|
T1 |
14 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12124772 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
522957 |
| auto[1] |
672663 |
1 |
|
|
T33 |
35946 |
|
T19 |
1 |
|
T1 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7472147 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
276814 |
| auto[1] |
5325288 |
1 |
|
|
T33 |
282089 |
|
T19 |
27 |
|
T1 |
54 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2328171 |
1 |
|
|
T33 |
121581 |
|
T19 |
21 |
|
T1 |
47 |
| auto[1] |
auto[0] |
auto[1] |
338831 |
1 |
|
|
T33 |
18003 |
|
T1 |
1 |
|
T12 |
1036 |
| auto[1] |
auto[1] |
auto[0] |
2324454 |
1 |
|
|
T33 |
124562 |
|
T19 |
5 |
|
T1 |
6 |
| auto[1] |
auto[1] |
auto[1] |
333832 |
1 |
|
|
T33 |
17943 |
|
T19 |
1 |
|
T12 |
1066 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7475343 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
275215 |
| auto[1] |
5322092 |
1 |
|
|
T33 |
283688 |
|
T19 |
48 |
|
T1 |
8 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12123257 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
523888 |
| auto[1] |
674178 |
1 |
|
|
T33 |
35015 |
|
T19 |
2 |
|
T1 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7466672 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
282401 |
| auto[1] |
5330763 |
1 |
|
|
T33 |
276502 |
|
T19 |
61 |
|
T1 |
26 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2344633 |
1 |
|
|
T33 |
117481 |
|
T19 |
35 |
|
T1 |
19 |
| auto[1] |
auto[0] |
auto[1] |
338575 |
1 |
|
|
T33 |
16760 |
|
T19 |
1 |
|
T1 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2311952 |
1 |
|
|
T33 |
124006 |
|
T19 |
24 |
|
T1 |
6 |
| auto[1] |
auto[1] |
auto[1] |
335603 |
1 |
|
|
T33 |
18255 |
|
T19 |
1 |
|
T12 |
828 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7482226 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
288046 |
| auto[1] |
5315209 |
1 |
|
|
T33 |
270857 |
|
T19 |
40 |
|
T1 |
33 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12123525 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
523600 |
| auto[1] |
673910 |
1 |
|
|
T33 |
35303 |
|
T19 |
1 |
|
T1 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7457722 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
282040 |
| auto[1] |
5339713 |
1 |
|
|
T33 |
276863 |
|
T19 |
49 |
|
T1 |
19 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2349558 |
1 |
|
|
T33 |
126415 |
|
T19 |
28 |
|
T1 |
4 |
| auto[1] |
auto[0] |
auto[1] |
339634 |
1 |
|
|
T33 |
18507 |
|
T12 |
933 |
|
T14 |
25 |
| auto[1] |
auto[1] |
auto[0] |
2316245 |
1 |
|
|
T33 |
115145 |
|
T19 |
20 |
|
T1 |
14 |
| auto[1] |
auto[1] |
auto[1] |
334276 |
1 |
|
|
T33 |
16796 |
|
T19 |
1 |
|
T1 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7447368 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
285376 |
| auto[1] |
5350067 |
1 |
|
|
T33 |
273527 |
|
T19 |
51 |
|
T1 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12125864 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
522041 |
| auto[1] |
671571 |
1 |
|
|
T33 |
36862 |
|
T12 |
1909 |
|
T14 |
36 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7479064 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
272945 |
| auto[1] |
5318371 |
1 |
|
|
T33 |
285958 |
|
T19 |
48 |
|
T1 |
33 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2328608 |
1 |
|
|
T33 |
128051 |
|
T19 |
30 |
|
T1 |
31 |
| auto[1] |
auto[0] |
auto[1] |
336872 |
1 |
|
|
T33 |
18819 |
|
T12 |
1054 |
|
T14 |
24 |
| auto[1] |
auto[1] |
auto[0] |
2318192 |
1 |
|
|
T33 |
121045 |
|
T19 |
18 |
|
T1 |
2 |
| auto[1] |
auto[1] |
auto[1] |
334699 |
1 |
|
|
T33 |
18043 |
|
T12 |
855 |
|
T14 |
12 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7460951 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
281896 |
| auto[1] |
5336484 |
1 |
|
|
T33 |
277007 |
|
T19 |
53 |
|
T1 |
33 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12124050 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
524067 |
| auto[1] |
673385 |
1 |
|
|
T33 |
34836 |
|
T19 |
1 |
|
T12 |
1866 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7469605 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
284491 |
| auto[1] |
5327830 |
1 |
|
|
T33 |
274412 |
|
T19 |
43 |
|
T1 |
17 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2321230 |
1 |
|
|
T33 |
120157 |
|
T19 |
32 |
|
T1 |
8 |
| auto[1] |
auto[0] |
auto[1] |
334373 |
1 |
|
|
T33 |
17605 |
|
T19 |
1 |
|
T12 |
1116 |
| auto[1] |
auto[1] |
auto[0] |
2333215 |
1 |
|
|
T33 |
119419 |
|
T19 |
10 |
|
T1 |
9 |
| auto[1] |
auto[1] |
auto[1] |
339012 |
1 |
|
|
T33 |
17231 |
|
T12 |
750 |
|
T14 |
13 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7484376 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
280785 |
| auto[1] |
5313059 |
1 |
|
|
T33 |
278118 |
|
T19 |
28 |
|
T1 |
39 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12125160 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
523333 |
| auto[1] |
672275 |
1 |
|
|
T33 |
35570 |
|
T19 |
1 |
|
T12 |
1905 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7469937 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
277962 |
| auto[1] |
5327498 |
1 |
|
|
T33 |
280941 |
|
T19 |
43 |
|
T1 |
27 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2344176 |
1 |
|
|
T33 |
123203 |
|
T19 |
37 |
|
T1 |
12 |
| auto[1] |
auto[0] |
auto[1] |
338588 |
1 |
|
|
T33 |
17877 |
|
T19 |
1 |
|
T12 |
954 |
| auto[1] |
auto[1] |
auto[0] |
2311047 |
1 |
|
|
T33 |
122168 |
|
T19 |
5 |
|
T1 |
15 |
| auto[1] |
auto[1] |
auto[1] |
333687 |
1 |
|
|
T33 |
17693 |
|
T12 |
951 |
|
T14 |
22 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7476936 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
283198 |
| auto[1] |
5320499 |
1 |
|
|
T33 |
275705 |
|
T19 |
54 |
|
T1 |
38 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12126167 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
523308 |
| auto[1] |
671268 |
1 |
|
|
T33 |
35595 |
|
T12 |
1967 |
|
T14 |
38 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7487653 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
279054 |
| auto[1] |
5309782 |
1 |
|
|
T33 |
279849 |
|
T19 |
22 |
|
T1 |
22 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2317996 |
1 |
|
|
T33 |
118492 |
|
T19 |
22 |
|
T1 |
13 |
| auto[1] |
auto[0] |
auto[1] |
335559 |
1 |
|
|
T33 |
17140 |
|
T12 |
768 |
|
T14 |
18 |
| auto[1] |
auto[1] |
auto[0] |
2320518 |
1 |
|
|
T33 |
125762 |
|
T1 |
9 |
|
T12 |
7803 |
| auto[1] |
auto[1] |
auto[1] |
335709 |
1 |
|
|
T33 |
18455 |
|
T12 |
1199 |
|
T14 |
20 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7441896 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
288588 |
| auto[1] |
5355539 |
1 |
|
|
T33 |
270315 |
|
T19 |
7 |
|
T1 |
21 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12124370 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
523865 |
| auto[1] |
673065 |
1 |
|
|
T33 |
35038 |
|
T1 |
1 |
|
T12 |
2102 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7478245 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
281071 |
| auto[1] |
5319190 |
1 |
|
|
T33 |
277832 |
|
T19 |
51 |
|
T1 |
39 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2318810 |
1 |
|
|
T33 |
125755 |
|
T19 |
50 |
|
T1 |
29 |
| auto[1] |
auto[0] |
auto[1] |
334532 |
1 |
|
|
T33 |
18115 |
|
T1 |
1 |
|
T12 |
1150 |
| auto[1] |
auto[1] |
auto[0] |
2327315 |
1 |
|
|
T33 |
117039 |
|
T19 |
1 |
|
T1 |
9 |
| auto[1] |
auto[1] |
auto[1] |
338533 |
1 |
|
|
T33 |
16923 |
|
T12 |
952 |
|
T14 |
21 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7459935 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
278872 |
| auto[1] |
5337500 |
1 |
|
|
T33 |
280031 |
|
T19 |
26 |
|
T1 |
44 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12121780 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
522246 |
| auto[1] |
675655 |
1 |
|
|
T33 |
36657 |
|
T19 |
1 |
|
T1 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7461266 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
273179 |
| auto[1] |
5336169 |
1 |
|
|
T33 |
285724 |
|
T19 |
58 |
|
T1 |
39 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2331750 |
1 |
|
|
T33 |
125234 |
|
T19 |
51 |
|
T1 |
15 |
| auto[1] |
auto[0] |
auto[1] |
337399 |
1 |
|
|
T33 |
18364 |
|
T19 |
1 |
|
T12 |
836 |
| auto[1] |
auto[1] |
auto[0] |
2328764 |
1 |
|
|
T33 |
123833 |
|
T19 |
6 |
|
T1 |
23 |
| auto[1] |
auto[1] |
auto[1] |
338256 |
1 |
|
|
T33 |
18293 |
|
T1 |
1 |
|
T12 |
989 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7476522 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
287854 |
| auto[1] |
5320913 |
1 |
|
|
T33 |
271049 |
|
T19 |
32 |
|
T1 |
13 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12124665 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
523863 |
| auto[1] |
672770 |
1 |
|
|
T33 |
35040 |
|
T12 |
1899 |
|
T14 |
44 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7479669 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
280892 |
| auto[1] |
5317766 |
1 |
|
|
T33 |
278011 |
|
T19 |
69 |
|
T1 |
10 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2328598 |
1 |
|
|
T33 |
124683 |
|
T19 |
54 |
|
T1 |
4 |
| auto[1] |
auto[0] |
auto[1] |
336649 |
1 |
|
|
T33 |
18062 |
|
T12 |
907 |
|
T14 |
25 |
| auto[1] |
auto[1] |
auto[0] |
2316398 |
1 |
|
|
T33 |
118288 |
|
T19 |
15 |
|
T1 |
6 |
| auto[1] |
auto[1] |
auto[1] |
336121 |
1 |
|
|
T33 |
16978 |
|
T12 |
992 |
|
T14 |
19 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7481869 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
282728 |
| auto[1] |
5315566 |
1 |
|
|
T33 |
276175 |
|
T19 |
40 |
|
T1 |
52 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12119774 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
523715 |
| auto[1] |
677661 |
1 |
|
|
T33 |
35188 |
|
T19 |
2 |
|
T12 |
1886 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7442550 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
281216 |
| auto[1] |
5354885 |
1 |
|
|
T33 |
277687 |
|
T19 |
45 |
|
T1 |
32 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2344933 |
1 |
|
|
T33 |
123646 |
|
T19 |
30 |
|
T1 |
10 |
| auto[1] |
auto[0] |
auto[1] |
339886 |
1 |
|
|
T33 |
17931 |
|
T19 |
1 |
|
T12 |
1080 |
| auto[1] |
auto[1] |
auto[0] |
2332291 |
1 |
|
|
T33 |
118853 |
|
T19 |
13 |
|
T1 |
22 |
| auto[1] |
auto[1] |
auto[1] |
337775 |
1 |
|
|
T33 |
17257 |
|
T19 |
1 |
|
T12 |
806 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7486173 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
273849 |
| auto[1] |
5311262 |
1 |
|
|
T33 |
285054 |
|
T19 |
36 |
|
T1 |
37 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12124218 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
523068 |
| auto[1] |
673217 |
1 |
|
|
T33 |
35835 |
|
T19 |
1 |
|
T12 |
1898 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7478290 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
278258 |
| auto[1] |
5319145 |
1 |
|
|
T33 |
280645 |
|
T19 |
44 |
|
T1 |
13 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2339830 |
1 |
|
|
T33 |
115963 |
|
T19 |
27 |
|
T1 |
8 |
| auto[1] |
auto[0] |
auto[1] |
338181 |
1 |
|
|
T33 |
16796 |
|
T12 |
893 |
|
T14 |
10 |
| auto[1] |
auto[1] |
auto[0] |
2306098 |
1 |
|
|
T33 |
128847 |
|
T19 |
16 |
|
T1 |
5 |
| auto[1] |
auto[1] |
auto[1] |
335036 |
1 |
|
|
T33 |
19039 |
|
T19 |
1 |
|
T12 |
1005 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7491806 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
283251 |
| auto[1] |
5305629 |
1 |
|
|
T33 |
275652 |
|
T19 |
50 |
|
T1 |
29 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12122801 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
522184 |
| auto[1] |
674634 |
1 |
|
|
T33 |
36719 |
|
T1 |
1 |
|
T12 |
1686 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7467945 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
273874 |
| auto[1] |
5329490 |
1 |
|
|
T33 |
285029 |
|
T19 |
40 |
|
T1 |
29 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2342870 |
1 |
|
|
T33 |
122084 |
|
T19 |
17 |
|
T1 |
20 |
| auto[1] |
auto[0] |
auto[1] |
339056 |
1 |
|
|
T33 |
17979 |
|
T12 |
850 |
|
T14 |
17 |
| auto[1] |
auto[1] |
auto[0] |
2311986 |
1 |
|
|
T33 |
126226 |
|
T19 |
23 |
|
T1 |
8 |
| auto[1] |
auto[1] |
auto[1] |
335578 |
1 |
|
|
T33 |
18740 |
|
T1 |
1 |
|
T12 |
836 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7469246 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
277443 |
| auto[1] |
5328189 |
1 |
|
|
T33 |
281460 |
|
T19 |
27 |
|
T1 |
30 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12122934 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
523430 |
| auto[1] |
674501 |
1 |
|
|
T33 |
35473 |
|
T19 |
2 |
|
T12 |
2023 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7462163 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
279951 |
| auto[1] |
5335272 |
1 |
|
|
T33 |
278952 |
|
T19 |
44 |
|
T1 |
20 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2333356 |
1 |
|
|
T33 |
121863 |
|
T19 |
32 |
|
T1 |
14 |
| auto[1] |
auto[0] |
auto[1] |
337446 |
1 |
|
|
T33 |
17759 |
|
T12 |
1035 |
|
T14 |
20 |
| auto[1] |
auto[1] |
auto[0] |
2327415 |
1 |
|
|
T33 |
121616 |
|
T19 |
10 |
|
T1 |
6 |
| auto[1] |
auto[1] |
auto[1] |
337055 |
1 |
|
|
T33 |
17714 |
|
T19 |
2 |
|
T12 |
988 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7460669 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
281362 |
| auto[1] |
5336766 |
1 |
|
|
T33 |
277541 |
|
T19 |
43 |
|
T1 |
27 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12121188 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
523604 |
| auto[1] |
676247 |
1 |
|
|
T33 |
35299 |
|
T19 |
1 |
|
T12 |
1947 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7448619 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
282001 |
| auto[1] |
5348816 |
1 |
|
|
T33 |
276902 |
|
T19 |
60 |
|
T1 |
17 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2331987 |
1 |
|
|
T33 |
120553 |
|
T19 |
43 |
|
T1 |
11 |
| auto[1] |
auto[0] |
auto[1] |
337012 |
1 |
|
|
T33 |
17509 |
|
T19 |
1 |
|
T12 |
900 |
| auto[1] |
auto[1] |
auto[0] |
2340582 |
1 |
|
|
T33 |
121050 |
|
T19 |
16 |
|
T1 |
6 |
| auto[1] |
auto[1] |
auto[1] |
339235 |
1 |
|
|
T33 |
17790 |
|
T12 |
1047 |
|
T14 |
34 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7474042 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
287070 |
| auto[1] |
5323393 |
1 |
|
|
T33 |
271833 |
|
T19 |
27 |
|
T1 |
33 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12126809 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
523272 |
| auto[1] |
670626 |
1 |
|
|
T33 |
35631 |
|
T19 |
1 |
|
T12 |
1946 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7481845 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
280227 |
| auto[1] |
5315590 |
1 |
|
|
T33 |
278676 |
|
T19 |
38 |
|
T1 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2342082 |
1 |
|
|
T33 |
125514 |
|
T19 |
32 |
|
T12 |
6585 |
| auto[1] |
auto[0] |
auto[1] |
338190 |
1 |
|
|
T33 |
18307 |
|
T19 |
1 |
|
T12 |
917 |
| auto[1] |
auto[1] |
auto[0] |
2302882 |
1 |
|
|
T33 |
117531 |
|
T19 |
5 |
|
T1 |
5 |
| auto[1] |
auto[1] |
auto[1] |
332436 |
1 |
|
|
T33 |
17324 |
|
T12 |
1029 |
|
T14 |
29 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7469894 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
287778 |
| auto[1] |
5327541 |
1 |
|
|
T33 |
271125 |
|
T19 |
24 |
|
T1 |
26 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12126389 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
524140 |
| auto[1] |
671046 |
1 |
|
|
T33 |
34763 |
|
T19 |
3 |
|
T1 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7485399 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
283245 |
| auto[1] |
5312036 |
1 |
|
|
T33 |
275658 |
|
T19 |
58 |
|
T1 |
34 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2323253 |
1 |
|
|
T33 |
120460 |
|
T19 |
42 |
|
T1 |
13 |
| auto[1] |
auto[0] |
auto[1] |
337024 |
1 |
|
|
T33 |
17488 |
|
T19 |
3 |
|
T12 |
882 |
| auto[1] |
auto[1] |
auto[0] |
2317737 |
1 |
|
|
T33 |
120435 |
|
T19 |
13 |
|
T1 |
20 |
| auto[1] |
auto[1] |
auto[1] |
334022 |
1 |
|
|
T33 |
17275 |
|
T1 |
1 |
|
T12 |
788 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7479932 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
278462 |
| auto[1] |
5317503 |
1 |
|
|
T33 |
280441 |
|
T19 |
60 |
|
T1 |
33 |