Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7468305 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
273185 |
| auto[1] |
5329130 |
1 |
|
|
T33 |
285718 |
|
T19 |
22 |
|
T1 |
30 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12123686 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
523677 |
| auto[1] |
673749 |
1 |
|
|
T33 |
35226 |
|
T19 |
2 |
|
T12 |
1918 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7466785 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
282320 |
| auto[1] |
5330650 |
1 |
|
|
T33 |
276583 |
|
T19 |
58 |
|
T1 |
12 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2342547 |
1 |
|
|
T33 |
117584 |
|
T19 |
50 |
|
T1 |
12 |
| auto[1] |
auto[0] |
auto[1] |
340185 |
1 |
|
|
T33 |
17027 |
|
T19 |
2 |
|
T12 |
1115 |
| auto[1] |
auto[1] |
auto[0] |
2314354 |
1 |
|
|
T33 |
123773 |
|
T19 |
6 |
|
T12 |
5438 |
| auto[1] |
auto[1] |
auto[1] |
333564 |
1 |
|
|
T33 |
18199 |
|
T12 |
803 |
|
T14 |
20 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |