Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7449964 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
272735 |
| auto[1] |
5347471 |
1 |
|
|
T33 |
286168 |
|
T19 |
46 |
|
T1 |
36 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12124247 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
523505 |
| auto[1] |
673188 |
1 |
|
|
T33 |
35398 |
|
T19 |
2 |
|
T1 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7468111 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
281465 |
| auto[1] |
5329324 |
1 |
|
|
T33 |
277438 |
|
T19 |
54 |
|
T1 |
32 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2329941 |
1 |
|
|
T33 |
120461 |
|
T19 |
35 |
|
T1 |
9 |
| auto[1] |
auto[0] |
auto[1] |
335754 |
1 |
|
|
T33 |
17486 |
|
T19 |
2 |
|
T12 |
864 |
| auto[1] |
auto[1] |
auto[0] |
2326195 |
1 |
|
|
T33 |
121579 |
|
T19 |
17 |
|
T1 |
22 |
| auto[1] |
auto[1] |
auto[1] |
337434 |
1 |
|
|
T33 |
17912 |
|
T1 |
1 |
|
T12 |
933 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |