Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7434466 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
280110 |
| auto[1] |
5362969 |
1 |
|
|
T33 |
278793 |
|
T19 |
21 |
|
T1 |
45 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12119812 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
522644 |
| auto[1] |
677623 |
1 |
|
|
T33 |
36259 |
|
T19 |
1 |
|
T12 |
1952 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7449553 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
274827 |
| auto[1] |
5347882 |
1 |
|
|
T33 |
284076 |
|
T19 |
60 |
|
T1 |
32 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2331986 |
1 |
|
|
T33 |
123183 |
|
T19 |
52 |
|
T1 |
17 |
| auto[1] |
auto[0] |
auto[1] |
337713 |
1 |
|
|
T33 |
17919 |
|
T19 |
1 |
|
T12 |
1048 |
| auto[1] |
auto[1] |
auto[0] |
2338273 |
1 |
|
|
T33 |
124634 |
|
T19 |
7 |
|
T1 |
15 |
| auto[1] |
auto[1] |
auto[1] |
339910 |
1 |
|
|
T33 |
18340 |
|
T12 |
904 |
|
T14 |
26 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |