Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7485977 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
283425 |
| auto[1] |
5311458 |
1 |
|
|
T33 |
275478 |
|
T19 |
13 |
|
T1 |
39 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12127423 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
523023 |
| auto[1] |
670012 |
1 |
|
|
T33 |
35880 |
|
T12 |
1775 |
|
T14 |
50 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7483917 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
276540 |
| auto[1] |
5313518 |
1 |
|
|
T33 |
282363 |
|
T19 |
49 |
|
T1 |
26 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2324975 |
1 |
|
|
T33 |
126320 |
|
T19 |
37 |
|
T1 |
19 |
| auto[1] |
auto[0] |
auto[1] |
334440 |
1 |
|
|
T33 |
18427 |
|
T12 |
814 |
|
T14 |
12 |
| auto[1] |
auto[1] |
auto[0] |
2318531 |
1 |
|
|
T33 |
120163 |
|
T19 |
12 |
|
T1 |
7 |
| auto[1] |
auto[1] |
auto[1] |
335572 |
1 |
|
|
T33 |
17453 |
|
T12 |
961 |
|
T14 |
38 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |