Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7501388 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
283999 |
| auto[1] |
5296047 |
1 |
|
|
T33 |
274904 |
|
T19 |
38 |
|
T1 |
38 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10612310 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
455457 |
| auto[1] |
2185125 |
1 |
|
|
T33 |
103446 |
|
T19 |
19 |
|
T1 |
18 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7475060 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
281432 |
| auto[1] |
5322375 |
1 |
|
|
T33 |
277471 |
|
T19 |
31 |
|
T1 |
23 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1588354 |
1 |
|
|
T33 |
88764 |
|
T19 |
8 |
|
T1 |
3 |
| auto[1] |
auto[0] |
auto[1] |
1103995 |
1 |
|
|
T33 |
52516 |
|
T19 |
15 |
|
T1 |
8 |
| auto[1] |
auto[1] |
auto[0] |
1548896 |
1 |
|
|
T33 |
85261 |
|
T19 |
4 |
|
T1 |
2 |
| auto[1] |
auto[1] |
auto[1] |
1081130 |
1 |
|
|
T33 |
50930 |
|
T19 |
4 |
|
T1 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |