Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7475343 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
275215 |
| auto[1] |
5322092 |
1 |
|
|
T33 |
283688 |
|
T19 |
48 |
|
T1 |
8 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10608499 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
456723 |
| auto[1] |
2188936 |
1 |
|
|
T33 |
102180 |
|
T19 |
2 |
|
T1 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7474039 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
289498 |
| auto[1] |
5323396 |
1 |
|
|
T33 |
269405 |
|
T19 |
27 |
|
T1 |
10 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1563455 |
1 |
|
|
T33 |
81065 |
|
T19 |
16 |
|
T1 |
1 |
| auto[1] |
auto[0] |
auto[1] |
1092358 |
1 |
|
|
T33 |
49430 |
|
T1 |
7 |
|
T12 |
4263 |
| auto[1] |
auto[1] |
auto[0] |
1571005 |
1 |
|
|
T33 |
86160 |
|
T19 |
9 |
|
T1 |
2 |
| auto[1] |
auto[1] |
auto[1] |
1096578 |
1 |
|
|
T33 |
52750 |
|
T19 |
2 |
|
T12 |
4283 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |