Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12127562 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
522882 |
| auto[1] |
669873 |
1 |
|
|
T33 |
36021 |
|
T19 |
2 |
|
T1 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7499797 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
275828 |
| auto[1] |
5297638 |
1 |
|
|
T33 |
283075 |
|
T19 |
52 |
|
T1 |
36 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2316612 |
1 |
|
|
T33 |
122842 |
|
T19 |
22 |
|
T1 |
20 |
| auto[1] |
auto[0] |
auto[1] |
335490 |
1 |
|
|
T33 |
17843 |
|
T1 |
1 |
|
T12 |
931 |
| auto[1] |
auto[1] |
auto[0] |
2311153 |
1 |
|
|
T33 |
124212 |
|
T19 |
28 |
|
T1 |
14 |
| auto[1] |
auto[1] |
auto[1] |
334383 |
1 |
|
|
T33 |
18178 |
|
T19 |
2 |
|
T1 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |